Abstract: A method for monitoring polishing process parameters for an integrated circuit structure on a substrate. A first metrology site is constructed on the substrate. The first metrology site represents a design extreme of a high density integrated circuit structure. The first metrology site is formed by placing a relatively small horizontal surface area trench within a relatively large surface area field of a polish stop material. A second metrology site is also constructed on the substrate. The second metrology site represents a design extreme of a low density integrated circuit structure. The second metrology site is formed by placing a relatively large horizontal surface area trench within a relatively small surface area field of a polish stop material. The substrate is covered with a layer of an insulating material, thereby at least filling the trenches.

Abstract: A method for monitoring polishing process parameters for an integrated circuit structure on a substrate. A first metrology site is constructed on the substrate. The first metrology site represents a design extreme of a high density integrated circuit structure. The first metrology site is formed by placing a relatively small horizontal surface area trench within a relatively large surface area field of a polish stop material. A second metrology site is also constructed on the substrate. The second metrology site represents a design extreme of a low density integrated circuit structure. The second metrology site is formed by placing a relatively large horizontal surface area trench within a relatively small surface area field of a polish stop material. The substrate is covered with a layer of an insulating material, thereby at least filling the trenches.

Abstract: Provided is a chemical mechanical polishing pad which as capable of draining used slurry from the polishing pad surface through the pad. Chemical mechanical polishing pads according to preferred embodiments of the present invention have slurry drain holes to drain slurry from the pad surface. In various preferred embodiments, the drain holes are combined with drain grooves in the pad surface and/or the pad/pad backing or pad/platen interface to provide a path for used slurry to exit the pad. The invention also provides a method of conducting CMP using through-pad slurry drainage.

Abstract: A method for forming an alignment feature on a substrate. The alignment feature is of the type concurrently formed with an electrically conductive layer overlying an electrically nonconductive layer having vias. The vias are filled with an electrically conductive material, and the alignment feature has a smaller aspect ratio than the vias. The alignment feature is not filled with the electrically conductive material when a first amount of the electrically conductive material, sufficient to just fill the vias, is deposited on the substrate. The first amount of the electrically conductive material within the alignment feature is not sufficient to prevent the alignment feature in the electrically conductive layer from distorting, and thereby reducing the effectiveness of the alignment feature. The improvement is in depositing an additional amount of the electrically conductive material on the substrate.

Abstract: A polishing pad surface having a surface designed for chemical mechanical polishing of a substrate surface is described. The polishing pad surface includes a first area on the surface exposed to and capable of contacting a first amount of the substrate surface during chemical-mechanical polishing and a second area on the surface exposed to and capable of contacting a second amount of the substrate surface during chemical-mechanical polishing, wherein the second amount is larger than the first amount of the substrate surface to produce a more uniformly polished substrate surface.

Abstract: A conditioning wafer for conditioning a polishing pad employed in chemical-mechanical polishing of an integrated circuit substrate is described. The conditioning wafer includes a disk having a conditioning surface and a plurality of abrasive particles secured on the conditioning surface of the disk. Furthermore, the abrasive particles engage with the polishing pad when the conditioning wafer contacts the polishing pad during conditioning of the polishing pad.

Abstract: A process of conditioning a polishing pad used in chemical mechanical polishing of an integrated circuit and having a glazed layer is described. The process includes introducing a conditioning reagent including at least one of hydrofluoric acid, buffered oxide etch composition and potassium hydroxide on the polishing pad to dissolve at least a portion of the glazed layer; and abrading the glazed layer and disloding at least some particles from the glazed layer.

Abstract: A polishing pad surface designed for chemical mechanical polishing of substrates is described. The polishing pad includes a first area of the surface having formed thereon a first set of grooves and a second area of the surface having formed thereon a second set of grooves, wherein the first set of grooves have a larger cross-sectional area than the second set of grooves.

Abstract: A method for determining the thickness of a film in a film stack using reflectance spectroscopy is provided in which one of the films in the stack has unknown optical constants. Conventional methods of using reflectance measurements to determine the thickness of a film require knowledge of the thicknesses and optical constants of all underlying films. An embodiment involves forming a test layer across a substrate having a known thickness and known optical constants. The thickness of the layer is determined using reflectance measurements. A first layer of the same material is then formed across a second layer at the same conditions that the test layer was formed. Thus, the test layer and the first layer can be assumed to have the same thicknesses. A spectral response curve may be determined for the first layer. The first layer is then processed so that its thickness is no longer known.