Abstract: A method and apparatus to adjust a differential transmitter output impedance is disclosed. Output voltage is sampled and averaged to mitigate noise and leakage. Averaged uplevel and downlevel voltages are used to select a number of pullup devices and a number of pulldown devices to control the differential transmitter output impedance to match a distal termination resistance or a transmission line impedance.

Abstract: A method and apparatus to adjust a differential transmitter output impedance is disclosed. Output voltage is sampled and averaged to mitigate noise and leakage. Averaged uplevel and downlevel voltages are used to select a number of pullup devices and a number of pulldown devices to control the differential transmitter output impedance to match a distal termination resistance or a transmission line impedance.

Abstract: A circuit component comprises a row of transistors. The row may contain a first active FET with a source region and a drain region. The row may also contain a first active dummy FET that shares the source region and that also has a diffusion region. The row may also contain a second active FET and a second active dummy FET, positioned such that the active dummy FETs are located between the active FETs on the row. The row may also have an end positioned such that the first active dummy FET is between the end and the first active FET. A supply of current may be electrically connected to the source diffusion regions. A load region may be electrically connected to the drain region. The first active FET and the first active dummy FET may have gates that share a voltage source or that have their own voltage source.

Abstract: The present disclosure discloses an IC with an electromigration (EM) monitor. The IC includes a functional circuit configured according to a first value of a parameter related to EM tolerance. The IC also includes a dummy version of the functional circuit configured according to a second value of the parameter. The second value causes the dummy version of the functional circuit to be more sensitive to an EM event than the functional circuit. Upon the EM monitor determines that the EM event occurs in the dummy version of the functional circuit, the EM monitor asserts a signal indicating that the EM event has occurred in the dummy version of the functional circuit and providing a warning that the EM event is likely to occur in the functional circuit.

Abstract: The present disclosure discloses an IC with an electromigration (EM) monitor. The IC includes a functional circuit configured according to a first value of a parameter related to EM tolerance. The IC also includes a dummy version of the functional circuit configured according to a second value of the parameter. The second value causes the dummy version of the functional circuit to be more sensitive to an EM event than the functional circuit. Upon the EM monitor determines that the EM event occurs in the dummy version of the functional circuit, the EM monitor asserts a signal indicating that the EM event has occurred in the dummy version of the functional circuit and providing a warning that the EM event is likely to occur in the functional circuit.

Abstract: Certain aspects of the present disclosure are directed to a circuit for driving a signal at an output node. The circuit generally includes a voltage divider network having a first terminal coupled to the output node. The circuit also includes a first transistor having a gate coupled to a second terminal of the voltage divider network and a plurality of transistors. A gate of each of the plurality of transistors may be coupled to a respective tap node of the voltage divider network, and the plurality of transistors may include a third transistor having a source coupled to a drain of the first transistor. The circuit may also include a second transistor coupled to the first transistor and having a gate coupled to an input node of the circuit.

Abstract: Certain aspects of the present disclosure are directed to a circuit for driving a signal at an output node. The circuit generally includes a voltage divider network having a first terminal coupled to the output node. The circuit also includes a first transistor having a gate coupled to a second terminal of the voltage divider network and a plurality of transistors. A gate of each of the plurality of transistors may be coupled to a respective tap node of the voltage divider network, and the plurality of transistors may include a third transistor having a source coupled to a drain of the first transistor. The circuit may also include a second transistor coupled to the first transistor and having a gate coupled to an input node of the circuit.

Abstract: A circuit component comprises a row of transistors. The row may contain a first active FET with a source region and a drain region. The row may also contain a first active dummy FET that shares the source region and that also has a diffusion region. The row may also contain a second active FET and a second active dummy FET, positioned such that the active dummy FETs are located between the active FETs on the row. The row may also have an end positioned such that the first active dummy FET is between the end and the first active FET. A supply of current may be electrically connected to the source diffusion regions. A load region may be electrically connected to the drain region. The first active FET and the first active dummy FET may have gates that share a voltage source or that have their own voltage source.

Abstract: A method and circuit are provided for implementing adaptive control for optimization of pulsed resonant drivers, and a design structure on which the subject circuit resides. Peak detectors are used to detect a positive or up level reached by a resonant clock and negative or down level reached by the resonant clock. Each detected levels is compared to a reference level to determine when to vary the turn off timing of a clock driver pull-up device and/or a clock driver pull-down device. A positive peak detector controls the turn off time of the pull-up device and a negative peak detector controls a turn off time of the pull-down device in the pulsed resonant driver.

Abstract: A method and circuit are provided for implementing adaptive control for optimization of pulsed resonant drivers, and a design structure on which the subject circuit resides. Peak detectors are used to detect a positive or up level reached by a resonant clock and negative or down level reached by the resonant clock. Each detected levels is compared to a reference level to determine when to vary the turn off timing of a clock driver pull-up device and/or a clock driver pull-down device. A positive peak detector controls the turn off time of the pull-up device and a negative peak detector controls a turn off time of the pull-down device in the pulsed resonant driver.

Abstract: A method and circuit are provided for implementing adaptive control for optimization of pulsed resonant drivers, and a design structure on which the subject circuit resides. Peak detectors are used to detect a positive or up level reached by a resonant clock and negative or down level reached by the resonant clock. Each detected levels is compared to a reference level to determine when to vary the turn off timing of a clock driver pull-up device and/or a clock driver pull-down device. A positive peak detector controls the turn off time of the pull-up device and a negative peak detector controls a turn off time of the pull-down device in the pulsed resonant driver.

Abstract: A method and circuit are provided for implementing adaptive control for optimization of pulsed resonant drivers, and a design structure on which the subject circuit resides. Peak detectors are used to detect a positive or up level reached by a resonant clock and negative or down level reached by the resonant clock. Each detected levels is compared to a reference level to determine when to vary the turn off timing of a clock driver pull-up device and/or a clock driver pull-down device. A positive peak detector controls the turn off time of the pull-up device and a negative peak detector controls a turn off time of the pull-down device in the pulsed resonant driver.

Abstract: A semiconductor chip device may include a silicon on insulator (SOI) base, a first transistor, and a voltage device. The SOI base may include a semiconductor substrate having a first doped layer and a second doped layer directly on the first doped layer, a buried oxide layer directly on the second doped layer, and a first moat electrically isolating a first bias region of the second doped layer. The first bias region may be electrically coupled to a current source. The first transistor may be formed above the buried oxide layer and the first bias region. The first transistor may include a first drain a first source a first body a first gate and a first back gate. The voltage device may be electrically coupled to the first back gate and the first gate and configured to maintain a voltage difference between the first gate and the first back gate.

Abstract: A semiconductor chip device may include a silicon on insulator (SOI) base, a first transistor, and a voltage device. The SOI base may include a semiconductor substrate having a first doped layer and a second doped layer directly on the first doped layer, a buried oxide layer directly on the second doped layer, and a first moat electrically isolating a first bias region of the second doped layer. The first bias region may be electrically coupled to a current source. The first transistor may be formed above the buried oxide layer and the first bias region. The first transistor may include a first drain a first source a first body a first gate and a first back gate. The voltage device may be electrically coupled to the first back gate and the first gate and configured to maintain a voltage difference between the first gate and the first back gate.

Abstract: A logic book for a programmable device such as an application-specific integrated circuit (ASIC) achieves improved radiation tolerance by providing notches in an implant well between adjacent transistors and fills the notches with complementary well regions that act as a barrier to charge migration. For example, a row of n-type field effect transistors (NFETs) is located in a Pwell region, while a row of p-type transistors is located in an Nwell region with portions of the Nwell region extending between the NFETs. More complicated embodiments of the present invention include embedded well islands to provide barriers for adjacent transistors in both rows of the book.

Abstract: A logic book for a programmable device such as an application-specific integrated circuit (ASIC) achieves improved radiation tolerance by providing transistors of the same doping type in different well regions that are physically isolated by intervening well regions with complementary doping. For example, n-type field effect transistors (NFETs) may be located in two outer rows of the book with separate Pwell regions, while p-type transistors are located in two inner rows of the book sharing a common Nwell region. Since the NFETs in separate wells are physically isolated from each other, a circuit structure which uses two NFETs in the two outer rows is much less likely to suffer multiple upsets from a single radiation strike. More complicated embodiments of the present invention include additional transistor rows in the stack with isolated Nwells and Pwells.

Abstract: A logic book for a programmable device such as an application-specific integrated circuit (ASIC) achieves improved radiation tolerance by providing notches in an implant well between adjacent transistors and fills the notches with complementary well regions that act as a barrier to charge migration. For example, a row of n-type field effect transistors (NFETs) is located in a Pwell region, while a row of p-type transistors is located in an Nwell region with portions of the Nwell region extending between the NFETs. More complicated embodiments of the present invention include embedded well islands to provide barriers for adjacent transistors in both rows of the book.

Abstract: A logic book for a programmable device such as an application-specific integrated circuit (ASIC) achieves improved radiation tolerance by providing transistors of the same doping type in different well regions that are physically isolated by intervening well regions with complementary doping. For example, n-type field effect transistors (NFETs) may be located in two outer rows of the book with separate Pwell regions, while p-type transistors are located in two inner rows of the book sharing a common Nwell region. Since the NFETs in separate wells are physically isolated from each other, a circuit structure which uses two NFETs in the two outer rows is much less likely to suffer multiple upsets from a single radiation strike. More complicated embodiments of the present invention include additional transistor rows in the stack with isolated Nwells and Pwells.