Abstract: Technologies for pluggable optical connectors are disclosed. In the illustrative embodiment, an optical plug includes a ferrule with one or more optical fibers. The optical plug also includes a ferrule holder that holds the ferrule and a housing that encloses the ferrule and ferrule holder. The ferrule holder can move relative to the house, and the ferrule can move relative to the ferrule holder and the housing. As the optical plug is plugged into a socket, alignment features in the housing coarsely align the ferrule. Intermediate alignment features in the ferrule holder then engage, aligning the ferrule more precisely. As the optical plug is fully plugged in, fine alignment features in the ferrule engage, precisely aligning the ferrule and the optical fibers with the optical socket.

Abstract: In one embodiment, an integrated circuit device includes a substrate, an electronic integrated circuit (EIC), a photonics integrated circuit (PIC) electrically coupled to the EIC, and a glass block at least partially in a cavity defined by the substrate and at an end of the substrate. The glass block defines an optical path with one or more optical elements to direct light between the PIC and a fiber array unit (FAU) when attached to the glass block.

Abstract: Optical connectors with alignment features, and methods of forming the same, are disclosed herein. In one example, an optical ferrule includes holes to couple a fiber array to the optical ferrule, a mating protrusion to mate with an optical receptacle, and alignment features to align the fiber array with optical waveguides in the optical receptacle. The optical receptacle includes the optical waveguides, a mating cavity to mate with the mating protrusion on the optical ferrule, and alignment features to mate with the alignment features on the optical ferrule.

Abstract: Technologies for beam expansion and collimation for photonic integrated circuits (PICs) are disclosed. In one embodiment, an ancillary die is bonded to a PIC die. Vertical couplers in the PIC die direct light from waveguides to flat mirrors on a top side of the ancillary die. The flat mirrors reflect the light towards curved mirrors defined in the bottom surface of the ancillary die. The curved mirrors collimate the light from the waveguides. In another embodiment, a cavity is formed in a PIC die, and curved mirrors are formed in the cavity. Light beams from waveguides in the PIC die are directed to the curved mirrors, which collimate the light beams.

Abstract: An electronic system and associated methods are disclosed. In one example, the electronic system includes a processor package including at least one processor integrated circuit (IC); an interposer including electrically conductive interposer interconnect; a first liquid metal well array including multiple liquid metal wells arranged between the processor package and the interposer, wherein the first liquid metal well array is attached to a surface of the processor package and attached to a first surface of the interposer and the interposer interconnect; a printed circuit board (PCB) attached to a second surface of the interposer and the interposer interconnect; a second liquid metal well array including a first surface attached to the first surface of the interposer and the interposer interconnect; and a first companion component package attached to a second surface of the second liquid metal well array.

Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes an integrated circuit (IC) package substrate including package interconnect and a first substrate surface; a processor IC attached to the first substrate surface and electrically connected to the package interconnect; a liquid metal well array including multiple liquid metal wells, a first array surface attached to the first substrate surface, and a second array surface; and a companion component to the processor IC attached to the second array surface of the liquid metal well array.

Abstract: An electronic system and associated methods are disclosed. In one example, the electronic system includes an interposer including electrically conductive interposer interconnect, a first interposer surface, and a second interposer surface; a processor package including at least one processor integrated circuit (IC), the processor package attached to the first interposer surface and electrically connected to the interposer interconnect; a first liquid metal well array including multiple liquid metal wells attached to a second interposer surface and the interposer interconnect; a second liquid metal well array including a first array surface attached to the first interposer surface and the interposer interconnect; and a packaged companion IC to the processor IC attached to a second array surface of the second liquid metal well array.

Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes liquid metal pathways that form one or more conduction pathway through one or more dielectric layers. In selected examples, the dielectric layers are resilient, which allows for flexibility of interconnect components.

Abstract: An electronic device comprises an electro-optical circuit package including at least photonic integrated circuit (PIC) having at least one light source and a package substrate; a printed circuit (PCB) including at least one optical connector to receive light from the at least one light source; and multiple liquid metal electrical contacts disposed between the package substrate and the PCB.

Abstract: Disclosed herein are embodiments of systems and methods for stable and elevated idle-mode temperature for assembled semiconductor devices. In an embodiment, a processor includes a communication interface configured to receive, from a first hardware component, instructions assigned to the processor for execution. The processor also includes temperature-measurement circuitry configured to monitor an on-chip temperature of the processor. The processor also includes control logic configured to: determine whether the processor is active or idle; determine whether the on-chip temperature of the processor exceeds a first threshold; based on determining that the processor is idle and that the on-chip temperature of the processor exceeds the first threshold, disable one or more idle-mode power-saving features of the processor; and selectively adjust one or more operating parameters of the processor to keep the on-chip temperature of the processor between the first threshold and a second (higher) threshold.

Abstract: In an optical circuit, a substrate can define a cavity that extends into a substrate front surface. A sidewall of the cavity can include a substrate optical port. An optical path can extend through the substrate from a connector optical port to the substrate optical port. A photonic integrated circuit (PIC) can attach to the substrate. A PIC front surface can include a plurality of electrical connections. A PIC edge surface can extend around at least a portion of a perimeter of the PIC between the PIC front surface and a PIC back surface. A PIC optical port can be disposed on the PIC edge surface and can accept or emit an optical beam along a PIC optical axis. The PIC optical axis can be aligned with the substrate optical port when the PIC is attached to the substrate.

Abstract: In an optical circuit, a substrate can have a substrate top surface, a substrate bottom surface, and a substrate edge surface that extends around at least a portion of a perimeter of the substrate. A photonic integrated circuit (PIC) can be attached to the substrate. The PIC can have a PIC optical port that is configured to accept or emit an optical beam along a PIC optical axis. A lens can be located at the substrate edge surface. The substrate can include an optical path that extends through the substrate from a first substrate optical port that is aligned with the PIC optical axis to a second substrate optical port that faces the lens, such that an optical beam emergent from the PIC optical port can traverse the optical path and pass through the lens to emerge substantially parallel to the substrate top surface.

Abstract: Embodiments of the present disclosure describe wafer-level die testing devices having a base with a planar X-Y surface, a plurality of thermal actuators situated on the surface, wherein one or more of the plurality of thermal actuators is movable in relation to the base in at least one of the X or the Y directions, and one or more adjustable links, wherein each adjustable link is to adjust a relative position between an individual thermal actuator of the plurality of thermal actuators and one or more other thermal actuators of the plurality of thermal actuators in one or more of the X or the Y directions. Other embodiments may be described and/or claimed.

Abstract: Embodiments of the present disclosure describe wafer-level die testing devices having a base with a planar X-Y surface, a plurality of thermal actuators situated on the surface, wherein one or more of the plurality of thermal actuators is movable in relation to the base in at least one of the X or the Y directions, and one or more adjustable links, wherein each adjustable link is to adjust a relative position between an individual thermal actuator of the plurality of thermal actuators and one or more other thermal actuators of the plurality of thermal actuators in one or more of the X or the Y directions. Other embodiments may be described and/or claimed.

Abstract: In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing fast throughput die handling for synchronous multi-die testing.

Abstract: Devices and methods useful for testing bare and packaged semiconductor dice are provided. As integrated circuit chips become smaller and increasingly complex, the interface presented by a chip for connectivity with power supplies and other components of the system into which it is integrated similarly becomes smaller and more complex. Embodiments of the invention provide micron-scale accuracy alignment capabilities for fine pitch device first level interconnect areas. Embodiments of the invention employ air-bearings to effectuate the movement and alignment of a device under test with a testing interface. Additionally, testing interfaces comprising membranes supported by thermal fluids are provided.

Abstract: Devices and methods useful for testing bare and packaged semiconductor dice are provided. As integrated circuit chips become smaller and increasingly complex, the interface presented by a chip for connectivity with power supplies and other components of the system into which it is integrated similarly becomes smaller and more complex. Embodiments of the invention provide micron-scale accuracy alignment capabilities for fine pitch device first level interconnect areas. Embodiments of the invention employ air-bearings to effectuate the movement and alignment of a device under test with a testing interface. Additionally, testing interfaces comprising membranes supported by thermal fluids are provided.

Abstract: In some embodiments, a temporary package for at-speed functional test of semiconductor chip, including high power chips, is presented. In this regard, a method is introduced including placing an integrated circuit die on a contactor layer, the contactor layer to electrically couple contacts on the integrated circuit die with contacts on a multi-layer substrate designed to be permanently attached with the integrated circuit die, placing an integrated heat spreader over the integrated circuit die, and bonding the integrated heat spreader with the substrate, the integrated heat spreader holding the integrated circuit die in place to form a temporary package. Other embodiments are also disclosed and claimed.

Abstract: In some embodiments, a temporary package for at-speed functional test of semiconductor chip, including high power chips, is presented. In this regard, a method is introduced including placing an integrated circuit die on a contactor layer, the contactor layer to electrically couple contacts on the integrated circuit die with contacts on a multi-layer substrate designed to be permanently attached with the integrated circuit die, placing an integrated heat spreader over the integrated circuit die, and bonding the integrated heat spreader with the substrate, the integrated heat spreader holding the integrated circuit die in place to form a temporary package. Other embodiments are also disclosed and claimed.