Patents by Inventor ERIC J. MORET

ERIC J. MORET has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230077633
    Abstract: An electronic device comprises a photonic integrated circuit (PIC) including at least one waveguide, an emitting lens disposed on the PIC to emit light from the at least one waveguide in a direction substantially parallel to a first surface of the PIC, and an optical element disposed on the PIC and having a reflective surface configured to direct light emitted from the emitting lens in a direction away from the first surface of the PIC.
    Type: Application
    Filed: September 15, 2021
    Publication date: March 16, 2023
    Inventors: Changhua Liu, Pooya Tadayon, John Heck, Eric J. Moret, Tarek A. Ibrahim, Zhichao Zhang, Jeremy D Ecton
  • Patent number: 9929031
    Abstract: A method includes identifying a wafer position for a plurality of die on a wafer, storing the wafer position for each of the plurality of die in a database, dicing the wafer into a plurality of singulated die, positioning each of the singulated die in a die position location on a tray, and storing the die position on the tray for each of the singulated die in the database. The database includes information including the wafer position associated with each die position. The tray is transported to a processing tool, and at least one of the plurality of singulated die is removed from the die position on the tray and processed in the processing tool. The processed singulated die is replaced in the same defined location on the tray that the singulated die was positioned in prior to the processing. Other embodiments are described and claimed.
    Type: Grant
    Filed: October 17, 2016
    Date of Patent: March 27, 2018
    Assignee: INTEL CORPORATION
    Inventors: John C. Johnson, Eric J. Moret, Lawrence M. Palanuk, Gregory A. Stone
  • Publication number: 20170032991
    Abstract: A method includes identifying a wafer position for a plurality of die on a wafer, storing the wafer position for each of the plurality of die in a database, dicing the wafer into a plurality of singulated die, positioning each of the singulated die in a die position location on a tray, and storing the die position on the tray for each of the singulated die in the database. The database includes information including the wafer position associated with each die position. The tray is transported to a processing tool, and at least one of the plurality of singulated die is removed from the die position on the tray and processed in the processing tool. The processed singulated die is replaced in the same defined location on the tray that the singulated die was positioned in prior to the processing. Other embodiments are described and claimed.
    Type: Application
    Filed: October 17, 2016
    Publication date: February 2, 2017
    Inventors: John C. JOHNSON, Sandeep B. SANE, Sandeep RAZDAN, Edward R. PRACK, Leonel R. ARANA, Peter A. DAVISON, Eric J. MORET, Lawrence M. PALANUK, Gregory A. STONE
  • Patent number: 9496161
    Abstract: A method includes identifying a wafer position for a plurality of die on a wafer, storing the wafer position for each of the plurality of die in a database, dicing the wafer into a plurality of singulated die, positioning each of the singulated die in a die position location on a tray, and storing the die position on the tray for each of the singulated die in the database. The database includes information including the wafer position associated with each die position. The tray is transported to a processing tool, and at least one of the plurality of singulated die is removed from the die position on the tray and processed in the processing tool. The processed singulated die is replaced in the same defined location on the tray that the singulated die was positioned in prior to the processing. Other embodiments are described and claimed.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: November 15, 2016
    Assignee: INTEL CORPORATION
    Inventors: John C. Johnson, Eric J. Moret, Lawrence M. Palanuk, Gregory A. Stone
  • Publication number: 20160172222
    Abstract: A method includes identifying a wafer position for a plurality of die on a wafer, storing the wafer position for each of the plurality of die in a database, dicing the wafer into a plurality of singulated die, positioning each of the singulated die in a die position location on a tray, and storing the die position on the tray for each of the singulated die in the database. The database includes information including the wafer position associated with each die position. The tray is transported to a processing tool, and at least one of the plurality of singulated die is removed from the die position on the tray and processed in the processing tool. The processed singulated die is replaced in the same defined location on the tray that the singulated die was positioned in prior to the processing. Other embodiments are described and claimed.
    Type: Application
    Filed: February 22, 2016
    Publication date: June 16, 2016
    Inventors: John C. JOHNSON, Sandeep B. SANE, Sandeep RAZDAN, Edward R. PRACK, Leonel R. ARANA, Peter A. DAVISON, Eric J. MORET, Lawrence M. PALANUK, Gregory A. STONE
  • Patent number: 9305816
    Abstract: A method includes identifying a wafer position for a plurality of die on a wafer, storing the wafer position for each of the plurality of die in a database, dicing the wafer into a plurality of singulated die, positioning each of the singulated die in a die position location on a tray, and storing the die position on the tray for each of the singulated die in the database. The database includes information including the wafer position associated with each die position. The tray is transported to a processing tool, and at least one of the plurality of singulated die is removed from the die position on the tray and processed in the processing tool. The processed singulated die is replaced in the same defined location on the tray that the singulated die was positioned in prior to the processing. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 28, 2013
    Date of Patent: April 5, 2016
    Assignee: INTEL CORPORATION
    Inventors: John C. Johnson, Peter A. Davison, Eric J. Moret, Lawrence M. Palanuk, Gregory A. Stone
  • Patent number: 9279854
    Abstract: A mechanism is described for facilitating and employing a modular processing cell framework according to one embodiment. A method of embodiments may include accepting one or more semiconductor devices in one or more media at a modular processing cell framework (“framework”) including a plurality of test cells, moving the one or more semiconductor devices from the one or more media to one or more test cells for testing; and testing the one or more semiconductor devices.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: March 8, 2016
    Assignee: Intel Corporation
    Inventors: John C. Johnson, Eric J. Moret, Robert W. Edmondson, Todd P. Albertson
  • Publication number: 20150187622
    Abstract: A method includes identifying a wafer position for a plurality of die on a wafer, storing the wafer position for each of the plurality of die in a database, dicing the wafer into a plurality of singulated die, positioning each of the singulated die in a die position location on a tray, and storing the die position on the tray for each of the singulated die in the database. The database includes information including the wafer position associated with each die position. The tray is transported to a processing tool, and at least one of the plurality of singulated die is removed from the die position on the tray and processed in the processing tool. The processed singulated die is replaced in the same defined location on the tray that the singulated die was positioned in prior to the processing. Other embodiments are described and claimed.
    Type: Application
    Filed: December 28, 2013
    Publication date: July 2, 2015
    Inventors: John C. JOHNSON, Sandeep B. SANE, Sandeep RAZDAN, Edward R. PRACK, Leonel R. ARANA, Peter A. DAVISON, Eric J. MORET, Lawrence M. PALANUK, Gregory A. STONE
  • Publication number: 20140184255
    Abstract: A mechanism is described for facilitating and employing a modular processing cell framework according to one embodiment. A method of embodiments may include accepting one or more semiconductor devices in one or more media at a modular processing cell framework (“framework”) including a plurality of test cells, moving the one or more semiconductor devices from the one or more media to one or more test cells for testing; and testing the one or more semiconductor devices.
    Type: Application
    Filed: December 28, 2012
    Publication date: July 3, 2014
    Inventors: JOHN C. JOHNSON, ERIC J. MORET, ROBERT W. EDMONDSON, TODD P. ALBERTSON