Patents by Inventor Eric J. Msechu

Eric J. Msechu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Requalization effort-balancing of transmit finite impulse response and receive linear equalizer or receive decision feedback equalizer structures in high-speed serial interconnects
    Patent number: 9325539
    Abstract: Methods and apparatus for provision of equalization effort-balancing of transmit (TX) Finite Impulse Response (FIR) and receive (RX) Linear Equalizer (LE) or RX Decision Feedback Equalizer (DFE) structures in high-speed serial interconnects are described. In some embodiments, data corresponding to a plurality of transmit equalization values and a plurality of receive equalization values for each lane of a link having a plurality of lanes is detected. At least one of the plurality of the transmit equalization values and at least one of the plurality of the receive equalization values are selected for each lane of the plurality of lanes of the link based on detection of saturation in a Decision Feedback Equalizer (DFE) tap of a corresponding lane of the link. Other embodiments are also claimed and/or disclosed.
    Type: Grant
    Filed: December 2, 2014
    Date of Patent: April 26, 2016
    Assignee: Intel Corporation
    Inventors: Manuel A. Aguilar-Arreola, Eric J. Msechu
  • REQUALIZATION EFFORT-BALANCING OF TRANSMIT FINITE IMPULSE RESPONSE AND RECEIVE LINEAR EQUALIZER OR RECEIVE DECISION FEEDBACK EQUALIZER STRUCTURES IN HIGH-SPEED SERIAL INTERCONNECTS
    Publication number: 20150249558
    Abstract: Methods and apparatus for provision of equalization effort-balancing of transmit (TX) Finite Impulse Response (FIR) and receive (RX) Linear Equalizer (LE) or RX Decision Feedback Equalizer (DFE) structures in high-speed serial interconnects are described. In some embodiments, data corresponding to a plurality of transmit equalization values and a plurality of receive equalization values for each lane of a link having a plurality of lanes is detected. At least one of the plurality of the transmit equalization values and at least one of the plurality of the receive equalization values are selected for each lane of the plurality of lanes of the link based on detection of saturation in a Decision Feedback Equalizer (DFE) tap of a corresponding lane of the link. Other embodiments are also claimed and/or disclosed.
    Type: Application
    Filed: December 2, 2014
    Publication date: September 3, 2015
    Inventors: MANUEL A. AGUILAR-ARREOLA, ERIC J. MSECHU
  • Equalization effort-balancing of transmit finite impulse response and receive linear equalizer or receive decision feedback equalizer structures in high-speed serial interconnects
    Patent number: 8902964
    Abstract: Methods and apparatus for provision of equalization effort-balancing of transmit (TX) Finite Impulse Response (FIR) and receive (RX) Linear Equalizer (LE) or RX Decision Feedback Equalizer (DFE) structures in high-speed serial interconnects are described. In some embodiments, data corresponding to a plurality of transmit equalization values and a plurality of receive equalization values for each lane of a link having a plurality of lanes is detected. At least one of the plurality of the transmit equalization values and at least one of the plurality of the receive equalization values are selected for each lane of the plurality of lanes of the link based on detection of saturation in a Decision Feedback Equalizer (DFE) tap of a corresponding lane of the link. Other embodiments are also claimed and/or disclosed.
    Type: Grant
    Filed: September 29, 2012
    Date of Patent: December 2, 2014
    Assignee: Intel Corporation
    Inventors: Manuel A. Aguilar-Arreola, Eric J. Msechu
  • EQUALIZATION EFFORT-BALANCING OF TRANSMIT FINITE IMPULSE RESPONSE AND RECEIVE LINEAR EQUALIZER OR RECEIVE DECISION FEEDBACK EQUALIZER STRUCTURES IN HIGH-SPEED SERIAL INTERCONNECTS
    Publication number: 20140092952
    Abstract: Methods and apparatus for provision of equalization effort-balancing of transmit (TX) Finite Impulse Response (FIR) and receive (RX) Linear Equalizer (LE) or RX Decision Feedback Equalizer (DFE) structures in high-speed serial interconnects are described. In some embodiments, data corresponding to a plurality of transmit equalization values and a plurality of receive equalization values for each lane of a link having a plurality of lanes is detected. At least one of the plurality of the transmit equalization values and at least one of the plurality of the receive equalization values are selected for each lane of the plurality of lanes of the link based on detection of saturation in a Decision Feedback Equalizer (DFE) tap of a corresponding lane of the link. Other embodiments are also claimed and/or disclosed.
    Type: Application
    Filed: September 29, 2012
    Publication date: April 3, 2014
    Inventors: Manuel A. Aguilar-Arreola, Eric J. Msechu