Abstract: A magnetoresistive memory device 20 includes dies 24 and 38, each of which contains magnetically sensitive material 50. A method 64 of packaging the magnetoresistive memory device 20 entails coupling the die 24 to a substrate 22, forming interconnections 52 between bonding pads 32 on the die 24 to connection sites 54 spaced apart from the die 24. A magnetic shield 36 is bonded to a top surface 30 of the die 24 following formation of the interconnections 52. The die 38 is attached to the magnetic shield 36, interconnections 56 are formed between bonding pads 44 on the die 38 to connection sites 58 spaced apart from the die 38, and a magnetic shield 48 is adhered to the die 38 following formation of the interconnections 56.

Abstract: A memory device, such an MRAM device, includes self-healing reference bits (104) associated with a set of array bits (102). The memory performs an error detection step (e.g., using an error-correction coding (ECC) algorithm, to detect the presence of a set of errors within the data bits. One of the reference bits (104) is toggled to a different state if an error count is greater than a predetermined threshold. If the set of errors remains unchanged when subsequently read, the reference bit (104) is toggled back to its original state.

Abstract: A shield structure for shielding an electromagnetic-field-susceptible region of a semiconductor component (e.g., a magnetoresistive random access memory, or “MRAM”) includes a stress-relief layer (e.g., electroplated Ni) formed over the semiconductor device in a shield region substantially corresponding to the electromagnetic-field-susceptible region, and a magnetic shield layer (e.g., an electroplated PERMALLOY or MUMETAL layer) mechanically coupled to the stress-relief layer within the shield region, wherein the magnetic shield layer has a stress condition that is substantially opposite of that of the stress-relief layer.

Abstract: A magnetoresistive memory device 20 includes dies 24 and 38, each of which contains magnetically sensitive material 50. A method 64 of packaging the magnetoresistive memory device 20 entails coupling the die 24 to a substrate 22, forming interconnections 52 between bonding pads 32 on the die 24 to connection sites 54 spaced apart from the die 24. A magnetic shield 36 is bonded to a top surface 30 of the die 24 following formation of the interconnections 52. The die 38 is attached to the magnetic shield 36, interconnections 56 are formed between bonding pads 44 on the die 38 to connection sites 58 spaced apart from the die 38, and a magnetic shield 48 is adhered to the die 38 following formation of the interconnections 56.

Abstract: A method of manufacturing a magnetoelectronic device includes providing an electrically conducting material and an electrically insulating material adjacent to at least a portion of the electrically conducting material, and implanting a magnetic material into the electrically insulating material. The magnetic material increases the magnetic permeability of the electrically insulating material. The implant may be a blanket or a targeted implant.

Abstract: According to an example embodiment, a method (500) includes applying a magnetic field to an array of Magnetic Tunnel Junction (MTJ) bits, a magnitude of the magnetic field sufficient to eliminate a stuck-at-mid condition exhibited by one of the MTJ bits without causing other ones of the MTJ bits to develop the stuck-at-mid condition.

Abstract: A shield structure for shielding an electromagnetic-field-susceptible region of a semiconductor component (e.g., a magnetoresistive random access memory, or “MRAM”) includes a stress-relief layer (e.g., electroplated Ni) formed over the semiconductor device in a shield region substantially corresponding to the electromagnetic-field-susceptible region, and a magnetic shield layer (e.g., an electroplated PERMALLOY or MUMETAL layer) mechanically coupled to the stress-relief layer within the shield region, wherein the magnetic shield layer has a stress condition that is substantially opposite of that of the stress-relief layer.

Abstract: An integrated circuit device includes a magnetic random access memory (“MRAM”) architecture and a smart power integrated circuit architecture formed on the same substrate using the same fabrication process technology. The fabrication process technology is a modular process having a front end process and a back end process. In the example embodiment, the smart power architecture includes a power circuit component, a digital logic component, and an analog control component formed by the front end process, and a sensor architecture formed by the back end process. The MRAM architecture includes an MRAM circuit component formed by the front end process and an MRAM cell array formed by the back end process. In one practical embodiment, the sensor architecture includes a sensor component that is formed from the same magnetic tunnel junction core material utilized by the MRAM cell array.

Abstract: An integrated circuit device (300) comprises a substrate (301) and MRAM architecture (314) formed on the substrate (308). The MRAM architecture (314) includes a MRAM circuit (318) formed on the substrate (301); and a MRAM cell (316) coupled to and formed above the MRAM circuit (318). Additionally a passive device (320) is formed in conjunction with the MRAM cell (316). The passive device (320) can be one or more resistors and one or more capacitor. The concurrent fabrication of the MRAM architecture (314) and the passive device (320) facilitates an efficient and cost effective use of the physical space available over active circuit blocks of the substrate (404, 504), resulting in three-dimensional integration.

Abstract: An integrated circuit device includes an active circuit component and a current sensor. The active circuit component may be coupled between a first conductive layer and a second conductive layer, and is configured to produce a first current. The current sensor is disposed over the active circuit component. The current sensor may includes a Magnetic Tunnel Junction (“MTJ”) core disposed between the first conductive layer and the second conductive layer. The MTJ core is configured to sense the first current and produce a second current based on the first current sensed at the MTJ core.

Abstract: A method to switch a scalable magnetoresistive memory cell including the steps of providing a magnetoresistive memory device (12) having two bits (18) and (20) sandwiched between a word line (14) and a digit line (16) so that current waveforms (104) and (106) can be applied to the word and digit lines at various times to cause a magnetic field flux HW and HD to rotate the effective magnetic moment vectors (86) and (94) of the device (12) by approximately 180°. Each bit includes N ferromagnetic layers (32) and (34, 42) and (44, 60) and (62, 72 and 74) that are anti-ferromagnetically coupled. N can be adjusted to change the magnetic switching volume of the bit. One or both bits may be programmed by adjusting the current in the word and/or digit lines.

Abstract: An analog to digital converter using a memory array of multi-state magnetoresistive memory elements in which a received analog signal is proportionally distributed among the memory elements to program the memory array. The memory array may be organized into column and row memory lines and may include analog splitter circuitry that proportionally distributes the analog signal among the column and row memory lines. The analog splitter circuitry may divide the analog signal into increasingly discrete signal levels along the column and row memory lines. The analog splitter circuitry may include multiple current devices, each configured to carry a proportionally increasing current level between consecutive column and row memory lines. Alternatively, the analog splitter circuitry includes substantially equivalent current devices that are grouped and proportionally distributed among the column and row memory lines to proportionally distribute the received analog signal.

Abstract: One or more multi-state magnetoresisitive memory elements (MRMEs) are used as the primary building block for various analog functional components implemented in corresponding analog functional modules. The MRMEs are configured into a memory array to create a programmable resistive element, a programmable voltage source, a programmable current source, an analog-to-digital converter (ADC), a digital-to-analog converter (DAC), a phase lock loop (PLL) and various other analog functional modules. The magnetoresistive analog functional modules are coupled together with at least one other logic module in a system to perform a process. When implemented on an IC, each module may each be implemented with the same or with different manufacturing processes. The other logic modules may be implemented in any desired manner, such as with magnetoresistive memory technology or any other type of technology providing complete system design flexibility.

Abstract: A system and method for programming a magnetoresistive memory array by applying current on a memory line aligned along the easy axis of the memory array, where the current generates a magnetic field that is independently sufficient to program at least two multi-state magnetoresistive memory elements coupled along the memory line. The memory array may be organized as one or more column memory lines along the easy axis and one or more row memory lines along a hard axis. In this configuration, the column drive circuitry includes a current source for each column memory line that is capable of programming all of the memory elements along the respective column memory line. Each column current source may assert a lesser or medium current level that generates a magnetic field that is insufficient alone to program the logic state of any memory element in the memory array.

Abstract: A programmable oscillator including a memory array of magnetoresistive memory elements, where the memory array is programmed to any one of multiple states based on one or more values and provides an output signal that controls a variable oscillator. The variable oscillator provides a frequency signal that corresponds to the output signal. The oscillator may be a voltage controlled oscillator (VCO) where the memory array is a voltage divider receiving a voltage reference signal and having a voltage junction that asserts a control voltage to the VCO. The voltage divider may include multiple voltage dividers, each including resistive circuits coupled on either side of the voltage junction and each programmed by a corresponding value. A frequency select register stores a frequency select value to program a frequency voltage divider. A trim select register stores a trim value to program a trim voltage divider.

Abstract: A programmable resistive circuit using magnetoresistive memory elements incorporated into one or more programmable segments coupled together between first and second terminals. Each segment includes at least one magnetoresistive memory element and at least one control input to select its state. The resistive circuit further includes select logic coupled to the control inputs of each segment to achieve a programmed resistance. A source signal is applied to the resistive circuit to develop an output signal that is a combination of signals developed by each of the memory elements in the resistive circuit. Bypass logic or switch devices may be included to selectively bypass or remove one or more segments. Each segment may include any combination of series and parallel coupled memory elements. The programmable segments may form a successive configuration to enable programming of progressive resistive values. The progressive resistive values may be linear and the successive configuration may be binary.

Abstract: A digital to analog converter using a memory array of multi-state magnetoresistive memory elements in which a number of the memory elements are programmed in proportion to a received digital input. A source selectively applies a reference signal to the programmed memory elements in the memory array, and an analog output signal is developed at an output terminal that combines signals developed by each of the memory elements. The reference signal may be a voltage or current signal, where the output signal is a current or voltage signal, respectively. The memory array may include column and row drive circuitry and control logic that controls the drive circuitry to program the memory array and assert the reference signal to develop the output signal. The control logic may be configured to program the memory array in successive steps by first programming one or more complete memory lines and then programming one or more partial memory lines.