Abstract: In an embodiment, an indicator is set to indicate that all of a plurality of most significant bytes of characters in a character array are zero. A first index and an input character are received. The input character comprises a first most significant byte and a first least significant byte. The first most significant byte is stored at a first storage location and the first least significant byte is stored at a second storage location, wherein the first storage location and the second storage location have non-contiguous addresses. If the first most significant byte does not equal zero, the indicator is set to indicate that at least one of a plurality of most significant bytes of the characters in the character array is non-zero. The character array comprises the first most significant byte and the first least significant byte.

Abstract: In an embodiment, an indicator is set to indicate that all of a plurality of most significant bytes of characters in a character array are zero. A first index and an input character are received. The input character comprises a first most significant byte and a first least significant byte. The first most significant byte is stored at a first storage location and the first least significant byte is stored at a second storage location, wherein the first storage location and the second storage location have non-contiguous addresses. If the first most significant byte does not equal zero, the indicator is set to indicate that at least one of a plurality of most significant bytes of the characters in the character array is non-zero. The character array comprises the first most significant byte and the first least significant byte.

Abstract: Call stack inspection for a thread of execution, including, for each stack frame in the call stack, beginning with the stack frame at the top of the call stack: inspecting the stack frame; determining whether the stack frame was present in the call stack on a previous inspection of the call stack; if the stack frame was not present on a previous inspection, indicating in the stack frame the stack frame's presence on the current inspection of the call stack; and if the stack frame was present on a previous inspection, notifying a user.

Abstract: A method, apparatus, and program product are provided for managing power consumption in a computer system based on the degree with which performance of tasks can be degraded in order to save power. A criticality value controls the degree with which performance of a task may be degraded is associated with tasks within a computer system. Power consumption of the computer system is then managed based on the criticality values associated with tasks executing within the computer system. A reduction in computer system power consumption can be realized by degrading the performance of non-critical tasks, which is accomplished by reducing the power consumed by at least a portion of the computer system. Power can also be reduced by scheduling non-critical tasks to portions of the computer system and reducing power consumption of other portions of the computer system.

Abstract: In an embodiment, an indicator is set to indicate that all of a plurality of most significant bytes of characters in a character array are zero. A first index and an input character are received. The input character comprises a first most significant byte and a first least significant byte. The first most significant byte is stored at a first storage location and the first least significant byte is stored at a second storage location, wherein the first storage location and the second storage location have non-contiguous addresses. If the first most significant byte does not equal zero, the indicator is set to indicate that at least one of a plurality of most significant bytes of the characters in the character array is non-zero. The character array comprises the first most significant byte and the first least significant byte.

Abstract: A method and circuit for eliminating silent store invalidation propagation in shared memory cache coherency protocols, and a design structure on which the subject circuit resides are provided. A received data value is compared with a stored cache data value. When the received data value matches the stored cache data value, a first squash signal is generated. A received write address is compared with a reservation address. When the received write address matches the reservation address, a reservation signal is generated and inverted. The first squash signal and the inverted reservation signal are combined to selectively produce a silent store squash signal. The silent store squash signal cancels sending an invalidation signal.

Abstract: Methods, systems and computer program products for CPU signaturing to aide in performance analysis. Exemplary embodiments include a performance analysis method including identifying a workload having one or more testcases, assigning a CPU signature to each of the one or more testcases, calling a CPU signature application programming interface that toggles the CPU to generate the CPU signature, passing four parameters to the CPU signature application programming interface, prior to running each of the one or more testcases of the workload, generating the CPU signature, dynamically determining a run order of the one or more testcases at a run time of the workload and reviewing performance data during the running of each of the one or more testcases, each of the one or more testcases being identifiable by its respective CPU signature.

Abstract: A method, apparatus, and program product are provided for managing power consumption in a computer system based on the degree with which performance of tasks can be degraded in order to save power. A criticality value controls the degree with which performance of a task may be degraded is associated with tasks within a computer system. Power consumption of the computer system is then managed based on the criticality values associated with tasks executing within the computer system. A reduction in computer system power consumption can be realized by degrading the performance of non-critical tasks, which is accomplished by reducing the power consumed by at least a portion of the computer system. Power can also be reduced by scheduling non-critical tasks to portions of the computer system and reducing power consumption of other portions of the computer system.

Abstract: Methods, systems and computer program products for CPU signaturing to aide in performance analysis. Exemplary embodiments include a performance analysis method including identifying a workload having one or more testcases, assigning a CPU signature to each of the one or more testcases, calling a CPU signature application programming interface that toggles the CPU to generate the CPU signature, passing four parameters to the CPU signature application programming interface, prior to running each of the one or more testcases of the workload, generating the CPU signature, dynamically determining a run order of the one or more testcases at a run time of the workload and reviewing performance data during the running of each of the one or more testcases, each of the one or more testcases being identifiable by its respective CPU signature.

Abstract: A method, system and computer program product for enabling retrieval and display from an information resource of additional information corresponding to an instant message (IM) contact using search topics detected/retrieved from: a profile of the IM contact; a stored list of topics of interest to the IM contact; and content manually selected from the contact's IM message during an ongoing IM session. The IM contact's profile information is entered by a local user or is received from the IM contact's IM client following an exchange of self-entered profile information between a local user and the IM contact during the IM session. A searching facility, when turned on, dynamically performs the search for additional information from the content retrieved from the profile. Returned information is then visually presented to the local user to enhance the local user's knowledge of the particular topic.

Abstract: A method, system and computer program product for enabling retrieval and display from an information resource of additional information corresponding to topics within current, real-time communication between an instant message (IM) contact and a local user. Content is dynamically (or manually) retrieved from the contact's IM message during an ongoing IM session/communication. A searching facility, when turned on, dynamically performs the search for additional information related to the content retrieved from within the communication exchanged during the on-going IM session. Returned information is then visually presented in real-time to the local user to enhance the local user's knowledge of the particular topic.

Abstract: A method and circuit for eliminating silent store invalidation propagation in shared memory cache coherency protocols, and a design structure on which the subject circuit resides are provided. A received write data value is compared with a stored cache data value. When the received write data value matches the stored cache data value, a first squash signal is generated. A received write address is compared with a reservation address. When the received write address matches the reservation address, a reservation signal is generated. The first squash signal and the reservation signal are combined to selectively produce a silent store squash signal. The silent store squash signal cancels sending an invalidation signal.