Abstract: A ferric nitrate-alumina based slurry useful for Chemical-Mechanical-Polishing of tungsten metallurgy and silica based oxides on semiconductor substrates in which the suspension and stability of abrasive material in the slurry is essentially stable. The slurry formulation is balanced to provide low residue of foreign material after polishing and due to its reduced ferric nitrate concentration will be less corrosive than prior art slurries. The recipe for the slurry includes of a 30% wt silica suspension, about 800 ml of 40% by wt ferric nonahydrate, liters and enough 70% wt nitric acid to adjust the pH of the slurry to about 1.2 to 1.4.

Abstract: A method of reworking copper metallurgy on semiconductor devices which includes selective removal of insulator, selective removal of copper, non-selective removal of copper and insulator followed by the redeposition of an insulating copper barrier layer and at least one metallurgical interconnect layer.

Abstract: A ferric nitrate-alumina based slurry useful for Chemical-Mechanical-Polishing of tungsten metallurgy and silica based oxides on semiconductor substrates in which the suspension and stability of abrasive material in the slurry is essentially stable. The slurry formulation is balanced to provide low residue of foreign material after polishing and due to its reduced ferric nitrate concentration will be less corrosive than prior art slurries. The recipe for the slurry includes of a 30% wt silica suspension, about 800 ml of 40% by wt ferric nonahydrate, liters and enough 70% wt nitric acid to adjust the pH of the slurry to about 1.2 to 1.4.

Abstract: A ferric nitrate-alumina based slurry useful for Chemical-Mechanical-Polishing of tungsten metallurgy and silica based oxides on semiconductor substrates in which the suspension and stability of abrasive material in the slurry is essentially stable. The slurry formulation is balanced to provide low residue of foreign material after polishing and due to its reduced ferric nitrate concentration will be less corrosive than prior art slurries. The recipe for the slurry includes of a 30% wt silica suspension, about 800 ml of 40% by wt ferric nonahydrate and enough 70% wt nitric acid to adjust the pH of the slurry to about 1.2 to 1.4.

Abstract: A method for forming a semiconductor structure includes supplying a structure having an exposed last metalization layer, cleaning the last metalization layer, forming a silicide in a top portion of the last metalization layer and forming a terminal over the silicide.

Abstract: In a chemical mechanical polishing process for planarization of semiconductor wafers, a pair of opposed grippers are used to move the wafer from one station to another. During this movement, the wafer is rotated and brushes along the periphery are placed in contact with the edge of the wafer to remove foreign material and residue which builds up along the edge of the wafer. Cleaning fluid may be introduced to flush away and/or breakup the residue buildup.

Abstract: A lead on chip (LOC) semiconductor leadframe package provides notched lead-fingers to eliminate mechanical shear-stress at the peripheral edge of a semiconductor chip. Opposite rows of substantially flat cantilevered lead-fingers are attached by double-sided adhesive tape in thermal contact with the active face of a chip. The lead-fingers are routed in personalized paths over the face of the chip to cover a large surface area to aid heat dissipation. All wirebond connections between the lead-fingers and the chip are made at a centerline connection strip running down the center of the chip. Each of the cantilevered lead-fingers has a notched portion positioned directly over the vulnerable peripheral chip edge to reduce thermal, mechanical shear-stress. Additionally, since corrosion typically follows a lead path, the notch provides increasing path length to prevent corrosive ingress over the chip face.

Abstract: A lead on chip (LOC) semiconductor leadframe package provides notched lead-fingers to eliminate mechanical shear-stress at the peripheral edge of a semiconductor chip. Opposite rows of substantially flat cantilevered lead-fingers are attached by double-sided adhesive tape in thermal contact with the active face of a chip. The lead-fingers are routed in personalized paths over the face of the chip to cover a large surface area to aid heat dissipation. All wirebond connections between the lead-fingers and the chip are made at a centerline connection strip running down the center of the chip. Each of the cantilevered lead-fingers has a notched portion positioned directly over the vulnerable peripheral chip edge to reduce thermal, mechanical shear-stress. Additionally, since corrosion typically follows a lead path, the notch provides an increasing path length to prevent corrosive ingress over the chip face.

Abstract: A process for making a crackstop on a semiconductor device is disclosed. The process involves creating and metallizing a groove surrounding the active region on a chip at the same time as other functional metallization is occurring, and then selectively etching out the metal in the groove after final passivation. In various embodiments the groove passes through the surface dielectric or the semiconductor substrate. In one embodiment the groove is replaced by hollow metal rings that can be stacked through multiple dielectric layers.

Abstract: A method is presented for controlled formation of microcavities for various semiconductor and micro-machine applications. The method involves the steps of defining a void in a support structure, sealing the void with a resilient gas-permeable material such that a chamber is formed, diffusing gas into the chamber through the gas permeable material to create a pressurized chamber, and then allowing expansion of the pressurized chamber within the resilient material, thereby creating an enlarged cavity. The applications set forth include the production of large capacitors, field isolation structures, tubular sensors for chromatography, pressure sensors, and cooling channels for integrated circuits.

Abstract: A method is presented for controlled formation of microcavities for various semiconductor and micro-machine applications. The method involves the steps of defining a void in a support structure, sealing the void with a resilient gas-permeable material such that a chamber is formed, diffusing gas into the chamber through the gas permeable material to create a pressurized chamber, and then allowing expansion of the pressurized chamber within the resilient material, thereby creating an enlarged cavity. The applications set forth include the production of large capacitors, field isolation structures, tubular sensors for chromatography, pressure sensors, and cooling channels for integrated circuits.

Abstract: A substantial reduction in the foreign particulate matter contamination on surfaces, such as the surfaces of semiconductor wafers, is achieved by treating the surfaces with a solution comprising a strong acid and a very small amount of a fluorine-containing compound. A preferred method employs a solution containing sulfuric acid, hydrogen peroxide and a very small amount of hydrofluoric acid, which is effective in reducing foreign particulate matter contamination, without significant etching, of the surface being treated.