Patents by Inventor Eric Jasinski
Eric Jasinski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8595557Abstract: A method for verifying the accuracy of memory testing software is disclosed. A built-in self test (BIST) fail control function is utilized to generate multiple simulated memory fails at various predetermined locations within a memory array of a memory device. The memory array is then tested by a memory tester. Afterwards, a bit fail map is generated by the logical-to-physical mapping software based on all the memory fails indicated by the memory tester. The bit fail map provides all the fail memory locations derived by the logical-to-physical mapping software. The fail memory locations derived by the logical-to-physical mapping software are then compared to the predetermined memory locations to verify the accuracy of the logical-to-physical mapping software.Type: GrantFiled: February 23, 2005Date of Patent: November 26, 2013Assignee: International Business Machines CorporationInventors: Eric Jasinski, Michael Richard Ouellette, Jeremy Paul Rowland
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Publication number: 20060190788Abstract: A method for verifying the accuracy of memory testing software is disclosed. A built-in self test (BIST) fail control function is utilized to generate multiple simulated memory fails at various predetermined locations within a memory array of a memory device. The memory array is then tested by a memory tester. Afterwards, a bit fail map is generated by the logical-to-physical mapping software based on all the memory fails indicated by the memory tester. The bit fail map provides all the fail memory locations derived by the logical-to-physical mapping software. The fail memory locations derived by the logical-to-physical mapping software are then compared to the predetermined memory locations to verify the accuracy of the logical-to-physical mapping software.Type: ApplicationFiled: February 23, 2005Publication date: August 24, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Eric Jasinski, Michael Ouellette, Jeremy Rowland
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Patent number: 6711040Abstract: A method and structure for improving a content addressable memory array has a plurality of serially connected memory sub-arrays (which include at least one memory cell), a matchline connected to each of the sub-arrays, a valid memory cell, a comparator receiving input from the matchline and valid memory cell, a sinkline output from the comparator, and a precharge device. The sinkline and matchline are reset from a first voltage to a second voltage depending upon the results of a compare operation of the input data to the data in the storage device. When the second voltage appears on the matchline and the first voltage appears on the sinkline this indicates a match between the data within all of the sub-arrays and the input data.Type: GrantFiled: January 28, 2003Date of Patent: March 23, 2004Assignee: International Business Machines CorporationInventors: Thomas B. Chadwick, Tari S. Gordon, Eric Jasinski, Rahul Nadkarni, Michael R. Quellette
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Publication number: 20030112648Abstract: A method and structure for improving a content addressable memory array has a plurality of serially connected memory sub-arrays (which include at least one memory cell), a matchline connected to each of the sub-arrays, a valid memory cell, a comparator receiving input from the matchline and valid memory cell, a sinkline output from the comparator, and a precharge device. The sinkline and matchline are reset from a first voltage to a second voltage depending upon the results of a compare operation of the input data to the data in the storage device. When the second voltage appears on the matchline and the first voltage appears on the sinkline this indicates a match between the data within all of the sub-arrays and the input data. If the second voltage appears on the sinkline this indicates a mismatch between data within any of the sub-arrays and the input data, or an invalid status within the valid memory cell and maintains the sinkline at the second voltage.Type: ApplicationFiled: January 28, 2003Publication date: June 19, 2003Inventors: Thomas B. Chadwick, Tarl S. Gordon, Eric Jasinski, Rahul Nadkarni, Michael R. Ouellette
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Patent number: 6552920Abstract: A method and structure for improving a content addressable memory array has a plurality of serially connected memory sub-arrays (which include at least one memory cell), a matchline connected to each of the sub-arrays, a valid memory cell, a comparator receiving input from the matchline and valid memory cell, a sinkline output from the comparator, and a precharge device. The sinkline and matchline are reset from a first voltage to a second voltage depending upon the results of a compare operation of the input data to the data in the storage device. When the second voltage appears on the matchline and the first voltage appears on the sinkline this indicates a match between the data within all of the sub-arrays and the input data.Type: GrantFiled: June 27, 2001Date of Patent: April 22, 2003Assignee: International Business Machines CorporationInventors: Thomas B. Chadwick, Tarl S. Gordon, Eric Jasinski, Rahul Nadkarni, Michael R. Ouellette
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Publication number: 20030002313Abstract: A method and structure for improving a content addressable memory array has a plurality of serially connected memory sub-arrays (which include at least one memory cell), a matchline connected to each of the sub-arrays, a valid memory cell, a comparator receiving input from the matchline and valid memory cell, a sinkline output from the comparator, and a precharge device. The sinkline and matchline are reset from a first voltage to a second voltage depending upon the results of a compare operation of the input data to the data in the storage device. When the second voltage appears on the matchline and the first voltage appears on the sinkline this indicates a match between the data within all of the sub-arrays and the input data. If the second voltage appears on the sinkline this indicates a mismatch between data within any of the sub-arrays and the input data, or an invalid status within the valid memory cell and maintains the sinkline at the second voltage.Type: ApplicationFiled: June 27, 2001Publication date: January 2, 2003Applicant: International Business Machines CorporationInventors: Thomas B. Chadwick, Tarl S. Gordon, Eric Jasinski, Rahul Nadkarni, Michael R. Ouellette
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Publication number: 20020101759Abstract: A memory cell layout provides for sharing of power supply connections between adjacent rows and columns of a memory array, respectively by providing a subarray layout in which one power connection is serpentine, extending into adjacent rows, and another stitches together a connection of memory cells in adjacent columns and adjacent rows. The subarray layout may be expanded by reflection and produced by lithographic exposures of relatively large numbers of memory cells in a step-and-repeat fashion. The layout of the power connections to the memory cells allows a significant reduction in the number of power connections required and/or the provision of redundant connections and a shielding mesh without increase of the number of connections required as well as full exploitation of minimum feature size with increased manufacturing yield.Type: ApplicationFiled: January 26, 2001Publication date: August 1, 2002Applicant: International Business Machines CorporationInventors: Eric Jasinski, Douglas W. Kemerer
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Patent number: 6426890Abstract: A memory cell layout provides for sharing of power supply connections between adjacent rows and columns of a memory array, respectively by providing a subarray layout in which one power connection is serpentine, extending into adjacent rows, and another stitches together a connection of memory cells in adjacent columns and adjacent rows. The subarray layout may be expanded by reflection and produced by lithographic exposures of relatively large numbers of memory cells in a step-and-repeat fashion. The layout of the power connections to the memory cells allows a significant reduction in the number of power connections required and/or the provision of redundant connections and a shielding mesh without increase of the number of connections required as well as full exploitation of minimum feature size with increased manufacturing yield.Type: GrantFiled: January 26, 2001Date of Patent: July 30, 2002Assignee: International Business Machines CorporationInventors: Eric Jasinski, Douglas W. Kemerer