Patents by Inventor Eric Jason Furbish

Eric Jason Furbish has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7644399
    Abstract: A list of program instructions are mapped into memory addresses to form an executable program by simulating their execution in turn so as to determine a memory address of a next program instruction to be executed. That memory address is then examined to determine if a program instruction has already been mapped thereto. If the memory address is empty, then the next program instruction from the list is mapped to that empty memory address and the execution of that next program instruction is simulated and the process repeated. If the memory address is not empty, then the program instruction read from that memory address is simulated again and the process repeated.
    Type: Grant
    Filed: December 3, 2004
    Date of Patent: January 5, 2010
    Assignee: ARM Limited
    Inventors: Simon John Craske, Eric Jason Furbish, Jonathan William Brawn
  • Patent number: 7444271
    Abstract: A test program for a data processing apparatus is produced using a genetic algorithm which mutates instances being ordered lists of program instructions within a population forming the test program. The populations are evaluated using a metric by which the population as a whole is scored for its stimulation of predetermined functional points within the data processing apparatus when a determination is being made as to whether or not a particular instance should be swapped in or out of the population.
    Type: Grant
    Filed: December 3, 2004
    Date of Patent: October 28, 2008
    Assignee: ARM Limited
    Inventors: Simon John Craske, Eric Jason Furbish, Jonathan William Brawn
  • Patent number: 7373550
    Abstract: Software built in self test computer programs 12 are generated using a genetic algorithm 14 technique. A fault simulator 20 is used to simulate candidate software built in self test computer programs and compare the simulated execution, such to deliberately introduced test faults, with expected execution outcomes previously derived for that candidate program to determine the sensitivity of that candidate program to the faults which are introduced. This score can be fed back into the genetic algorithm mutation to converge the mutation process upon appropriately fault sensitive software built in self test program code.
    Type: Grant
    Filed: February 3, 2005
    Date of Patent: May 13, 2008
    Assignee: ARM Limited
    Inventors: Jonathan William Brawn, Simon John Craske, Peter Logan Harrod, Eric Jason Furbish