Abstract: A graphics controller providing for efficient pixel value transformations. A graphics controller interfaces between a host and a graphics display device for displaying pixels having pixel values. The graphics controller includes a solarizing circuit having means for transforming an original pixel value to a transformed pixel value according to a transform function, said transform function having a negative slope at said original pixel value.

Abstract: A method and graphics controller for processing an image is provided wherein color filter array (CFA) data representing the image is received from a digital image capture device into a buffer, a digital filter effect is applied to the CFA data to generate filtered CFA data representing a filtered image, and the filtered image is displayed in real time on a display.

Abstract: A system is disclosed that provides a goal based learning system utilizing a rule based expert training system to provide a cognitive educational experience. The system provides the user with a simulated environment that presents a business opportunity to understand and solve optimally. Mistakes are noted and remedial educational material presented dynamically to build the necessary skills that a user requires for success in the business endeavor. The system utilizes an artificial intelligence engine driving individualized and dynamic feedback with synchronized video and graphics used to simulate real-world environment and interactions. Multiple “correct” answers are integrated into the learning system to allow individual learning experiences in which navigation through the system is at a pace controlled by the learner.

Abstract: A system is disclosed that provides a goal based learning system utilizing a rule based expert training system to provide a cognitive educational experience. The system provides the user with a simulated environment that presents a training opportunity to understand and solve optimally. Mistakes are noted and remedial educational material presented dynamically to build the necessary skills that a user requires for success in the business endeavor. The system uses an artificial intelligence engine driving individualized and dynamic feedback with synchronized video and graphics used to simulate real-world environment and interactions. Multiple “correct” answers are integrated into the learning system to allow individualized learning experiences in which navigation through the system is at a pace controlled by the learner.

Abstract: A method for concurrently displaying an image and a video on a display having memory integrated therein comprises receiving position data defining a position of a top image region, receiving video data from a video source, and passing the video data directly to the display, i.e., without first storing the image within video RAM. In a first mode video data is passed directly to the display only when it corresponds to pixels outside of the top image region. In a second mode, video data is passed directly to the display such that entire successive images are wholly displayed within the top image region. The top image region is smaller than the entire display region.

Abstract: A graphics controller for flicker filtering interlaced image data is provided. The graphics controller includes a buffer and a memory region. A flicker filter for reducing a flicker of a display presented through an interlaced scan is also provided. The flicker filter is configured to receive interlaced image data prior to any received image data being stored in the memory region. The flicker filter outputs filtered data defining a pixel. The filtered data is stored in the memory region such that two pixels can be output in one memory access to the memory region. Flicker filter enabling circuitry in communication with the buffer is provided. The flicker filter enabling circuitry is configured to supply an even segment and a corresponding odd segment of the interlaced image data to the flicker filter. An apparatus and methods for processing and storing image data having an interlaced format are also provided.

Abstract: A graphics controller including a memory and a contrast adjustment module is provided to perform on-board histogram stretching. The memory is configured to store a histogram table for a digital image. The contrast adjustment module is configured to read the histogram table stored in the memory and compute a histogram stretching transfer function based on the read histogram table. The contrast adjustment module is further configured to apply the computed histogram stretching transfer function to digital image data to be subsequently received by the contrast adjustment module.

Abstract: A digital imaging device is operated to capture a first image in a digital format. At least two non-contiguous portions of the first image are rendered in a display of the digital imaging device. The at least two non-contiguous portions of the first image are used to align a live version of a second image in the display, wherein the second image is an extension of the first image. The second image is captured in a digital format. A corner matching algorithm is applied to determine an offset of the second image with respect to the first image, wherein the offset is required to achieve a substantially accurate alignment of the first and second images. Application of the corner matching algorithm is limited to an overlap region intervening between the at least two non-contiguous portions of the first image.

Abstract: A hardware implemented method for interpolating missing colors is provided. In this method, the missing colors of a raw image received from an image capture device are interpolated using a first interpolation algorithm if the raw image is to be displayed on a display panel. It should be appreciated that the raw image is obtained through a color filter array. However, if the raw image is destined for output to a host, the missing colors of the raw image are interpolated using a second interpolation algorithm. An apparatus and a display controller for interpolating missing colors are also described.

Abstract: The invention is directed to specifying addresses in a memory for each sample in a minimum coded unit. Preferably, the samples are presented in a predetermined sequence to the memory for storage. For each sample, its presentation to the memory is detected and an offset parameter is provided. Addresses are specified by adding the offset parameter to a base address. When addresses are created for all of the samples that define a particular pixel, all of the addresses are for locations in a particular row of the memory. This allows the samples that define a pixel to be read in one or two read operations.

Abstract: The invention is directed to a method and apparatus for transforming the dimensions of an image represented by block-interleaved data. The method comprises: (a) storing a first minimum coded unit of the image data in a first memory; (b) dimensionally transforming the first minimum coded unit; and (c) storing a second minimum coded unit of the image data in the first memory. Steps (b) and (c) are performed after step (a). In addition, step (b) is performed before: starting to store any third minimum coded unit in the memory after step (c). The apparatus comprises a first memory, a storing circuit, a dimensional transforming circuit, and a timing control circuit. Preferably, the first memory is sized for storing no more than two minimum coded units.

Abstract: Histogram circuitry is provided to increment a tonal value tally corresponding to received pixel data without immediately writing the incremented tally back to a histogram table within a main memory. Instead, the tonal value and corresponding incremented tonal value tally are stored in a temporary memory of the histogram circuitry. Since received pixel data has a high likelihood of having the same tonal value as recently received pixel data, the tonal value of the received pixel data is first checked for a match with one of the recently received tonal values stored in the temporary memory. If the received tonal value is present in the temporary memory, there is no need to access the histogram table within the main memory to retrieve the corresponding tally. The tally corresponding to the received tonal value can simply be incremented in the temporary memory of the histogram circuitry.

Abstract: A display controller for sharing a memory between display data and compressed display data is provided. The display controller includes the memory, and the memory has a memory block configured to alternate between storing the display data and storing the compressed display data. A codec in communication with the memory block is also included in the display controller, whereby the codec is configured to generate the compressed display data from the display data stored in the first memory block. A hardware implemented method and an apparatus for sharing a memory between display data and compressed display data are also described.

Abstract: The invention is directed to a method and apparatus for storing image data received in a block-interleaved format using an MCU buffer. A first minimum coded unit of the image data is stored in a first memory. The image data in the first minimum coded unit is grouped into pixels. The grouped image data is stored in a second memory as a second minimum coded unit of the image data. Preferably, the image data is converted from a first color format to a second color format. Further, the image is preferably dimensionally transformed.

Abstract: A hardware implemented method for incorporating a border region within an image region is provided. In this method, a portion of the border region is stored in memory. Thereafter, a determination is made as to a relative position of a pixel within the image region. An image pixel or each pixel of the portion of the border region is then fetched from the memory dependent upon the relative position of the pixel. An apparatus and display controller for incorporating a border region within an image region are also described.

Abstract: The invention is directed to a method and apparatus for serially receiving and dimensionally transforming an image in an ordered sequence of interleaved blocks. Each block comprises an ordered sequence of samples of the image, and the samples of a single block all corresponding to a single color component. The method includes steps of counting the samples in the order received to determine a sequence number for each sample, comparing the sequence number with a set of predetermined values; and dimensionally transforming the image by either discarding the sample or storing the sample in a memory depending on the result of the comparison.

Abstract: A hardware implemented method for incorporating a border region within an image region is provided. In this hardware implemented method, a main image fetching circuit is accessed to determine a relative position of a pixel within the image region. Subsequently, an image pixel or a border pixel is fetched dependent upon the relative position of the pixel. An apparatus and display controllers for incorporating the border region within the image region also are described.

Abstract: A method and associated apparatus is provided for displaying a live image in a display window without corruption or loss of image data. More specifically, the method and associated apparatus maintain consistency between a size of an image to be displayed and a size of a display window in which the image is to be displayed. The method requires implementation of dimension value changes associated with the image to be displayed and the display window to be delayed until all required dimension value changes have been stored in a memory. Upon completion of storing each required dimension value change in the memory, a size change completion signal is provided by setting an enable bit within the memory. Upon receipt of a trigger signal while the enable bit is set, the dimension value changes associated with the image to be displayed and the display window are implemented together.

Abstract: A data pipeline and clock control (relationship) that allows image data from a camera to pass directly through a display controller to an LCD without being written into, temporarily stored, and read out of a display buffer, e.g. a VRAM, is provided. Elimination of the video memory (VRAM) lowers the chip cost, reduces the power requirements, reduces delay due to writing and reading from the video memory, and reduces the pin count since fewer power pins are required.

Abstract: A graphics controller for preparing data to be presented on a display through an interlaced scan is provided. The graphics controller includes a memory and a line buffer adapted to receive video data. Data arrangement circuitry in communication with the line buffer is included. The data arrangement circuitry is configured to process the received video data in order to store the received data in the memory as an even segment and a corresponding odd segment, the even segment associated with data from a line of an even field, the odd segment associated with data from a line of an odd field, the even segment and the corresponding odd segment defining a pixel of data. A single pipe buffer configured to retrieve the even segment and the corresponding odd segment in a single memory access to the memory is included. A system using the graphics controller and a method of storing and retrieving pixel data from memory are also provided.