Patents by Inventor Eric Jin Li

Eric Jin Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11545441
    Abstract: Semiconductor packages and package assemblies having active dies and external die mounts on a silicon wafer, and methods of fabricating such semiconductor packages and package assemblies, are described. In an example, a semiconductor package assembly includes a semiconductor package having an active die attached to a silicon wafer by a first solder bump. A second solder bump is on the silicon wafer laterally outward from the active die to provide a mount for an external die. An epoxy layer may surround the active die and cover the silicon wafer. A hole may extend through the epoxy layer above the second solder bump to expose the second solder bump through the hole. Accordingly, an external memory die can be connected directly to the second solder bump on the silicon wafer through the hole.
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: January 3, 2023
    Assignee: Intel Corporation
    Inventors: Vipul Vijay Mehta, Eric Jin Li, Sanka Ganesan, Debendra Mallik, Robert Leon Sankman
  • Publication number: 20210082826
    Abstract: Semiconductor packages and package assemblies having active dies and external die mounts on a silicon wafer, and methods of fabricating such semiconductor packages and package assemblies, are described. In an example, a semiconductor package assembly includes a semiconductor package having an active die attached to a silicon wafer by a first solder bump. A second solder bump is on the silicon wafer laterally outward from the active die to provide a mount for an external die. An epoxy layer may surround the active die and cover the silicon wafer. A hole may extend through the epoxy layer above the second solder bump to expose the second solder bump through the hole. Accordingly, an external memory die can be connected directly to the second solder bump on the silicon wafer through the hole.
    Type: Application
    Filed: November 24, 2020
    Publication date: March 18, 2021
    Inventors: Vipul Vijay MEHTA, Eric Jin LI, Sanka GANESAN, Debendra MALLIK, Robert Leon SANKMAN
  • Patent number: 10910317
    Abstract: Semiconductor packages and package assemblies having active dies and external die mounts on a silicon wafer, and methods of fabricating such semiconductor packages and package assemblies, are described. In an example, a semiconductor package assembly includes a semiconductor package having an active die attached to a silicon wafer by a first solder bump. A second solder bump is on the silicon wafer laterally outward from the active die to provide a mount for an external die. An epoxy layer may surround the active die and cover the silicon wafer. A hole may extend through the epoxy layer above the second solder bump to expose the second solder bump through the hole. Accordingly, an external memory die can be connected directly to the second solder bump on the silicon wafer through the hole.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: February 2, 2021
    Assignee: Intel Corporation
    Inventors: Vipul Vijay Mehta, Eric Jin Li, Sanka Ganesan, Debendra Mallik, Robert Leon Sankman
  • Publication number: 20190279938
    Abstract: Semiconductor packages and package assemblies having active dies and external die mounts on a silicon wafer, and methods of fabricating such semiconductor packages and package assemblies, are described. In an example, a semiconductor package assembly includes a semiconductor package having an active die attached to a silicon wafer by a first solder bump. A second solder bump is on the silicon wafer laterally outward from the active die to provide a mount for an external die. An epoxy layer may surround the active die and cover the silicon wafer. A hole may extend through the epoxy layer above the second solder bump to expose the second solder bump through the hole. Accordingly, an external memory die can be connected directly to the second solder bump on the silicon wafer through the hole.
    Type: Application
    Filed: December 29, 2016
    Publication date: September 12, 2019
    Inventors: Vipul Vijay MEHTA, Eric Jin LI, Sanka GANESAN, Debendra MALLIK, Robert Leon SANKMAN
  • Patent number: 9991211
    Abstract: Semiconductor packages and methods of forming semiconductor packages are described. In an example, a semiconductor package includes a shielding layer containing metal particles, e.g., conductive particles or magnetic particles, in a resin matrix to attenuate electromagnetic interference. In an example, the shielding layer is transferred from a molding chase to the semiconductor package during a polymer molding operation.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: June 5, 2018
    Assignee: Intel Corporation
    Inventors: Anna M. Prakash, Reynaldo Alberto Olmedo, Venmathy McMahan, Rajendra C. Dias, Joshua David Heppner, Ann Jinyan Xu, Sriya Sanyal, Eric Jin Li
  • Publication number: 20170287851
    Abstract: Semiconductor packages and methods of forming semiconductor packages are described. In an example, a semiconductor package includes a shielding layer containing metal particles, e.g., conductive particles or magnetic particles, in a resin matrix to attenuate electromagnetic interference. In an example, the shielding layer is transferred from a molding chase to the semiconductor package during a polymer molding operation.
    Type: Application
    Filed: May 26, 2017
    Publication date: October 5, 2017
    Inventors: Anna M. Prakash, Reynaldo Alberto Olmedo, Venmathy McMahan, Rajendra C. Dias, Joshua David Heppner, Ann Jinyan Xu, Sriya Sanyal, Eric Jin Li
  • Patent number: 9685413
    Abstract: Semiconductor packages and methods of forming semiconductor packages are described. In an example, a semiconductor package includes a shielding layer containing metal particles, e.g., conductive particles or magnetic particles, in a resin matrix to attenuate electromagnetic interference. In an example, the shielding layer is transferred from a molding chase to the semiconductor package during a polymer molding operation.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: June 20, 2017
    Assignee: Intel Corporation
    Inventors: Anna M. Prakash, Reynaldo Alberto Olmedo, Venmathy McMahan, Rajendra C. Dias, Joshua David Heppner, Ann Jinyan Xu, Sriya Sanyal, Eric Jin Li