Abstract: A semiconductor device having a memory array includes memory cells (101-104), a word line (42), a first bit line (68), and a second bit line (76). Within the memory array, the first and second bit lines (68 and 76) lie at different elevations above the word line (42). Local interconnects (58) are electrically connected to the first bit line (68) and some of the current carrying electrodes (48) in the memory array. The local interconnects (58) allow offset connections to be made. For floating gate memory cells (101-104) in a NOR-type memory array architecture, programming and erasing can be performed using a relatively uniform bias between the source and drain regions (46 and 48) of a memory cell (101) to be programmed without significantly disturbing data in adjacent floating gate memory cells (102-104).

Abstract: A voltage regulator with automatic accelerated aging circuit (200) includes a comparator (202), a switched voltage divider (204), and a current-to-voltage converter (224). The voltage regulator (200) is implemented in an integrated circuit and monitors a power supply voltage provided to the integrated circuit. When the power supply voltage is within a first normal voltage range, the voltage regulator (200) provides a normal internal supply voltage to the integrated circuit. When the power supply voltage is within a second higher voltage range, the voltage regulator (200) automatically provides a higher than normal internal power supply voltage to the circuits of an integrated circuit for causing accelerated aging of the integrated circuit during burn-in reliability testing.