Patents by Inventor Eric Johan Tell

Eric Johan Tell has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Data processing without processor core intervention by chain of accelerators selectively coupled by programmable interconnect network and to memory
    Patent number: 7415595
    Abstract: A programmable digital signal processor includes a plurality of memory units, a plurality of accelerator units and a processor core. The digital signal processor also includes a programmable network that may be configured to selectively provide connectivity between the memory units, the accelerator units, and the processor core. Each of the accelerator units may be configured to perform one or more dedicated functions. The processor core may include an execution unit that may be configured to execute instructions that are associated with datapath flow control. The programmable network may be configured to selectively provide the connectivity in response to execution of particular instructions.
    Type: Grant
    Filed: May 24, 2005
    Date of Patent: August 19, 2008
    Assignee: Coresonic AB
    Inventors: Eric Johan Tell, Anders Henrik Nilsson, Dake Liu
  • Complex vector executing clustered SIMD micro-architecture DSP with accelerator coupled complex ALU paths each further including short multiplier/accumulator using two's complement
    Patent number: 7299342
    Abstract: A programmable digital signal processor including a clustered SIMD microarchitecture includes a plurality of accelerator units, a processor core and a complex computing unit. Each of the accelerator units may be configured to perform one or more dedicated functions. The processor core includes an integer execution unit that may be configured to execute integer instructions. The complex computing unit may be configured to execute complex vector instructions. The complex computing unit may include a first and a second clustered execution pipeline. The first clustered execution pipeline may include one or more complex arithmetic logic unit datapaths configured to execute first complex vector instructions. The second clustered execution pipeline may include one or more complex multiplier accumulator datapaths configured to execute second complex vector instructions.
    Type: Grant
    Filed: August 11, 2005
    Date of Patent: November 20, 2007
    Assignee: Coresonic AB
    Inventors: Anders Henrik Nilsson, Eric Johan Tell, Dake Liu