Patents by Inventor Eric John Lukes
Eric John Lukes has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11804828Abstract: Aspects of the invention include receiving, by a controller, an indication of a chip initialization for a duty cycle correction (DCC) circuit, wherein the duty cycle correction circuit includes a main path including a main multiplexer (MUX) having a first input and a main driver circuit, a replica path including a replica MUX having a second input and a replica driver circuit, a selection MUX connected to the main path and the replica path, operating the selection MUX, during a period for the chip initialization, to select the main path as an input to the selection MUX, inputting a pre-defined data pattern to the main path, comparing an output of the selection MUX with the pre-defined data pattern to determine duty cycle issue, and generating an adjustment vector based on the determined duty cycle issue.Type: GrantFiled: February 22, 2022Date of Patent: October 31, 2023Assignee: International Business Machines CorporationInventors: Jieming Qi, Daniel Mark Dreps, Glen A. Wiedemeier, Eric John Lukes, Carrie Ellen Cox, Timothy O. Dickson
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Publication number: 20230268908Abstract: Aspects of the invention include receiving, by a controller, an indication of a chip initialization for a duty cycle correction (DCC) circuit, wherein the duty cycle correction circuit includes a main path including a main multiplexer (MUX) having a first input and a main driver circuit, a replica path including a replica MUX having a second input and a replica driver circuit, a selection MUX connected to the main path and the replica path, operating the selection MUX, during a period for the chip initialization, to select the main path as an input to the selection MUX, inputting a pre-defined data pattern to the main path, comparing an output of the selection MUX with the pre-defined data pattern to determine duty cycle issue, and generating an adjustment vector based on the determined duty cycle issue.Type: ApplicationFiled: February 22, 2022Publication date: August 24, 2023Inventors: Jieming Qi, Daniel Mark Dreps, Glen A. Wiedemeier, Eric John Lukes, Carrie Ellen Cox, Timothy O. Dickson
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Patent number: 7760843Abstract: The present invention provides for a self-correcting state circuit. A first flip flop is configured to receive a clock input and a first data input, and to generate a first output in response to the clock input and the first data input. A second flip flop is coupled to the first flip flop and configured to receive the clock input and to receive the first output as a second data input, and to generate a second output in response to the clock input and the first output. A first correction circuit is coupled to the second flip flop and configured to generate a corrected output. A third flip flop is coupled to the first correction circuit and configured to receive the clock input and to receive the corrected output as a third data input, and to generate a third output in response to the clock input and the third data input.Type: GrantFiled: August 7, 2008Date of Patent: July 20, 2010Assignee: International Business Machines CorporationInventors: David William Boerstler, Eric John Lukes, Hiroki Kihara, James David Strom
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Publication number: 20080301503Abstract: The present invention provides for a self-correcting state circuit. A first flip flop is configured to receive a clock input and a first data input, and to generate a first output in response to the clock input and the first data input. A second flip flop is coupled to the first flip flop and configured to receive the clock input and to receive the first output as a second data input, and to generate a second output in response to the clock input and the first output. A first correction circuit is coupled to the second flip flop and configured to generate a corrected output. A third flip flop is coupled to the first correction circuit and configured to receive the clock input and to receive the corrected output as a third data input, and to generate a third output in response to the clock input and the third data input.Type: ApplicationFiled: August 7, 2008Publication date: December 4, 2008Inventors: David William Boerstler, Eric John Lukes, Hiroki Kihara, James David Strom
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Patent number: 7453293Abstract: The present invention provides for a self-correcting state circuit. A first flip flop is configured to receive a clock input and a first data input, and to generate a first output in response to the clock input and the first data input. A second flip flop is coupled to the first flip flop and configured to receive the clock input and to receive the first output as a second data input, and to generate a second output in response to the clock input and the first output. A first correction circuit is coupled to the second flip flop and configured to generate a corrected output. A third flip flop is coupled to the first correction circuit and configured to receive the clock input and to receive the corrected output as a third data input, and to generate a third output in response to the clock input and the third data input.Type: GrantFiled: August 29, 2006Date of Patent: November 18, 2008Assignee: International Business Machines CorporationInventors: David William Boerstler, Eric John Lukes, Hiroki Kihara, James David Strom
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Publication number: 20080266925Abstract: A design structure including a semiconductor storage array having a first array portion on a first plane of circuitry and a second array portion on a second plane of circuitry. A composite bit line and/or a composite word line is divided and arranged to have a first portion on the first array portion and a second portion on the second array portion. The two portions of the composite word line or the composite bit line are on different planes of circuitry, and three-dimensional interconnections connect proximal ends of the word line portions, or proximal ends of the bit line portions. A word line driver drives the word line portions in parallel. A bit line driver drives the bit line portions in parallel. Signal propagation times down the composite word or bit lines are significantly less than signal propagation times down corresponding undivided word or bit lines.Type: ApplicationFiled: October 10, 2007Publication date: October 30, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Eric John Lukes, Nghia Van Phan
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Patent number: 7420832Abstract: A semiconductor storage array has a first array portion on a first plane of circuitry and a second array portion on a second plane of circuitry. A composite bit line and/or a composite word line is divided and arranged to have a first portion on the first array portion and a second portion on the second array portion. The two portions of the composite word line or the composite bit line are on different planes of circuitry, and three-dimensional interconnections connect proximal ends of the word line portions, or proximal ends of the bit line portions. A word line driver drives the word line portions in parallel. A bit line driver drives the bit line portions in parallel. Signal propagation times down the composite word or bit lines are significantly less than signal propagation times down corresponding undivided word or bit lines.Type: GrantFiled: April 30, 2007Date of Patent: September 2, 2008Assignee: International Business Machines CorporationInventors: Eric John Lukes, Nghia Van Phan
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Patent number: 7119587Abstract: The present invention provides for state correction. A first value in a state circuit is received from a flip flop. The received value is transmitted to a second flip flop. The received value within the second flip flop is altered if an error condition arises. The received value is transmitted to a third flip flop. In one aspect, the received value transmitted to the third flip flop comprises an unaltered received value. In another aspect, the received value transmitted to the third flip flop comprises transmitting an altered received value. This allows for an incorrect state within the state machine to change to a correct state after a few clock pulses.Type: GrantFiled: May 20, 2004Date of Patent: October 10, 2006Assignee: International Business Machines CorporationInventors: David William Boerstler, Eric John Lukes, Hiroki Kihara, James David Strom
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Patent number: 7061284Abstract: The present invention provides for state correction. A first flip flop coupled to a second flip flop. A state correction circuit coupled to the output of the second flip flop. A third flip flop is coupled to the output of the state correction circuit. A fourth flip flop is coupled to the output of the third flip flop.Type: GrantFiled: May 20, 2004Date of Patent: June 13, 2006Assignee: International Business Machines CorporationInventors: David William Boerstler, Eric John Lukes, Hiroki Kihara, James David Strom
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Patent number: 6973155Abstract: The present invention provides for a divider circuit for reducing anomalous output timing pulses. A latch is coupled to the division selection line. A comparator is coupled to the division selection line. A first synchronizer coupled to the output of the latch. A frequency divider is coupled to the output of the synchronizer. A second synchronizer is coupled to the output of the comparator and the output of the frequency divider. There is feedback between the output of the second synchronizer and the enable input of the latch, the reset of the first synchronizer, the reset of the second synchronized, and the reset of the divide by n divider.Type: GrantFiled: March 25, 2004Date of Patent: December 6, 2005Assignee: International Business Machines CorporationInventors: David William Boerstler, Eskinder Hailu, Eric John Lukes
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Patent number: 6859092Abstract: A method and a low voltage, complementary metal oxide semiconductor (CMOS) circuit are provided for generating voltage and current references with a low voltage power supply. A voltage generating circuit provides a voltage reference and is formed by a plurality of CMOS transistors and a resistor. An operational amplifier includes a differential pair of CMOS transistors. The first voltage reference is applied to an input of the differential pair of transistors and an output of the differential pair of transistors providing a second voltage reference. The operational amplifier includes a plurality of current reference transistors. A first voltage generating circuit generates a first voltage and a second voltage generating circuit generating a second voltage. The first and second voltage generating circuits are formed by a plurality of CMOS transistors. The generated first and second voltages are applied to the voltage reference generating circuit and current reference transistors.Type: GrantFiled: April 17, 2003Date of Patent: February 22, 2005Assignee: International Business Machines CorporationInventors: Eric John Lukes, Patrick Lee Rosno, James David Strom, Dana Marie Woeste
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Publication number: 20040207460Abstract: A method and a low voltage, complementary metal oxide semiconductor (CMOS) circuit are provided for generating voltage and current references with a low voltage power supply. A voltage generating circuit provides a voltage reference and is formed by a plurality of CMOS transistors and a resistor. An operational amplifier includes a differential pair of CMOS transistors. The first voltage reference is applied to an input of the differential pair of transistors and an output of the differential pair of transistors providing a second voltage reference. The operational amplifier includes a plurality of current reference transistors. A first voltage generating circuit generates a first voltage and a second voltage generating circuit generating a second voltage. The first and second voltage generating circuits are formed by a plurality of CMOS transistors. The generated first and second voltages are applied to the voltage reference generating circuit and current reference transistors.Type: ApplicationFiled: April 17, 2003Publication date: October 21, 2004Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Eric John Lukes, Patrick Lee Rosno, James David Strom, Dana Marie Woeste
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Patent number: 6670655Abstract: A method and apparatus are provided for implementing a body contact in a silicon-on-insulator field effect transistor device. A SOI field effect transistor is provided having a body contact having a predefined resistance that provides a higher device threshold voltage in the SOI FET device. A body of the SOI field effect transistor is connected to the gate of the SOI field effect transistor. The body gate connection of the SOI field effect transistor effectively lowers the device threshold voltage due to body bias effect. The SOI field effect transistor with a body connected to the gate of the SOI field effect transistor is used in circuits having stacked devices and DC currents. The SOI field effect transistor with a body connected to the gate of the SOI field effect transistor also is used in analog circuits with device matching requirements and in circuits having a low voltage power supply.Type: GrantFiled: April 18, 2001Date of Patent: December 30, 2003Assignee: International Business Machines CorporationInventors: Eric John Lukes, Patrick Lee Rosno, James David Strom
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Publication number: 20020155671Abstract: A method and apparatus are provided for implementing a body contact in a silicon-on-insulator field effect transistor device. A SOI field effect transistor is provided having a body contact having a predefined resistance that provides a higher device threshold voltage in the SOI FET device. A body of the SOI field effect transistor is connected to the gate of the SOI field effect transistor. The body gate connection of the SOI field effect transistor effectively lowers the device threshold voltage due to body bias effect. The SOI field effect transistor with a body connected to the gate of the SOI field effect transistor is used in circuits having stacked devices and DC currents. The SOI field effect transistor with a body connected to the gate of the SOI field effect transistor also is used in analog circuits with device matching requirements and in circuits having a low voltage power supply.Type: ApplicationFiled: April 18, 2001Publication date: October 24, 2002Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Eric John Lukes, Patrick Lee Rosno, James David Strom
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Patent number: 6342793Abstract: A CMOS signal transmission system for sending a large amount of CMOS signals into a separate quiet analog power domain. Transmission system comprises a converter sub-system which provides at least another device stage through which noise in the CMOS signals must flow and be attenuated to provide converted CMOS signals and a multiplexer coupled to the converter wherein the multiplexer receives converted CMOS signals from the converter sub-system and also receives delayed path control signals. The converter comprises a constant current source for providing a high level voltage reference and a constant current, two complimentary pass gates, and two sets of components for providing paths to ground from the constant current source through the two complimentary pass gates.Type: GrantFiled: November 3, 1999Date of Patent: January 29, 2002Assignee: International Business Machines CorporationInventors: Eric John Lukes, James David Strom, Dana Marie Woeste
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Patent number: 6218901Abstract: A high speed differential output driver is provided with increased voltage swing and predrive common mode adjustment. The high speed differential output driver includes a differential input with a voltage amplifier receiving the differential input signal and a common mode adjustment signal and providing an adjustable voltage amplified signal. An emitter follower is coupled to the voltage amplifier. The emitter follower provides a level shifted voltage amplified signal. A driver is coupled to the emitter follower receiving the level shifted voltage amplified signal and providing a driver output signal.Type: GrantFiled: October 12, 1999Date of Patent: April 17, 2001Assignee: International Business Machines CorporationInventors: Eric John Lukes, James David Strom, Dana Marie Woeste
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Patent number: 5903195Abstract: An improved phase locked loop (PLL) circuit is provided for use in microprocessor clock generation. A ring oscillator provides an output frequency signal. A voltage to current converter converts differential control voltages to a variable reference current applied to the ring oscillator. A range control reference current generator applies a range control reference current to the ring oscillator. A range control operatively controls the range control reference current generator to sequentially change the range control reference current applied to the ring oscillator. A lock detector coupled to the range control compares the output frequency signal and a reference frequency signal and responsive to the compares signals applies a locked signal to the range control. Responsive to an applied locked signal, the range control stops changing ranges. The phase locked loop (PLL) circuit automatically sweeps through multiple frequency subranges responsive to the range control.Type: GrantFiled: January 30, 1998Date of Patent: May 11, 1999Assignee: International Business Machines CorporationInventors: Eric John Lukes, James David Strom, Dana Marie Woeste
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Patent number: 5831484Abstract: A differential charge pump is provided for use with phase locked loop (PLL) circuits including a differential loop filter and a common mode bias circuit for maintaining a predetermined bias voltage value on a high voltage filter side of the loop filter. The differential charge pump includes a reference current source. First and second current mirrors are coupled to the reference current source for providing a first mirror current and a second mirror current. A first switching transistor coupled to the first current mirror receives an input UP signal conducts current from a first side of the loop filter. A second switching transistor coupled to the second current mirror receives an input DOWN signal and conducts current from a second side of the loop filter. The first and second current mirror and switching transistors are formed by N-channel metal oxide semiconductor (NMOS) devices. The differential charge pump enables a large differential output voltage with low phase error.Type: GrantFiled: March 18, 1997Date of Patent: November 3, 1998Assignee: International Business Machines CorporationInventors: Eric John Lukes, James David Strom