Abstract: In some embodiments, a device for transporting memory transactions over an Ethernet network, may include a first interface, a second interface, and a circuit. The first interface may be configured to communicate with a host device. The second interface may be configured to exchange Ethernet packets with the Ethernet network. The circuit may be coupled to the first interface and the second interface and configured to packetize one or more memory transaction requests received from the first interface, into a first Ethernet packet. The circuit may be configured to transmit, via the second interface to the Ethernet network, the first Ethernet packet. The circuit may be configured to depacketize a second Ethernet packet received from the second interface, into one or more memory transaction responses. The circuit may be configured to transmit, via the first interface to the host device, the one or more memory transaction responses.

Abstract: In some embodiments, a device may include a circuit configured to send a plurality of packets, each corresponding to one or more memory transactions and including a respective packet sequence number (PSN). The circuit may receive a first packet from an endpoint, determine a first expected packet sequence number (EPSN) of the first packet and a first PSN included in the first packet. In response to determining that the first EPSN is equal to the first PSN, update the first EPSN to a second ESPN, the circuit may send, to the endpoint, an acknowledgement (ACK) message identifying the second EPSN and indicating the first packet is an in-order packet. In response to determining that the first ESPN is not equal to the first PSN, the circuit may send, to the endpoint, a negative acknowledgement (NACK) message identifying the first EPSN and indicating the first packet is an out-of-order packet.

Abstract: A device may include a network interface configured to exchange Ethernet frames with an interconnection switch and circuitry coupled to the network interface. The circuitry may be configured to, for an Ethernet frame including a layer-two header and a payload, modify the layer-two header to include first information in a destination address field of the layer-two header. The first information may be addressing information used by the interconnection switch to forward the Ethernet frame. The circuitry may be configured to transmit, via the network interface to the interconnection switch, the Ethernet frame including the modified layer-two header.

Abstract: Fault tolerant and redundant grand master clock scheme may reduce or eliminate precision time transition caused by a network link or device failure. A primary synchronization message may be sent by a primary grandmaster clock and one or more backup synchronization message may be sent by respective backup grandmaster clocks. The primary and backup grandmaster clocks may be concurrently operated. The primary and backup synchronization messages may be sent to an end station over a network. The end station may derive a local clock based on one, some, or all of the received messages. The end station may or may not distinguish between the messages based on the clock source. The end station may validate messages received from a particular clock source.

Abstract: Devices implement encapsulation to support link layer preemption. The device may include a encapsulation logic that encapsulates data, such as an Ethernet frame, to produce an encapsulated frame. The encapsulated frame may include an encapsulation element that indicates whether the encapsulated data includes non-preemptible data, such as Distinguished Minimum Latency Traffic (DMLT), or preemptible data. The encapsulated frame may also indicate whether the encapsulated data comprises the last fragment of a preemptible frame.

Abstract: Fault tolerant and redundant grand master clock scheme may reduce or eliminate precision time transition caused by a network link or device failure. A primary synchronization message may be sent by a primary grandmaster clock and one or more backup synchronization message may be sent by respective backup grandmaster clocks. The primary and backup grandmaster clocks may be concurrently operated. The primary and backup synchronization messages may be sent to an end station over a network. The end station may derive a local clock based on one, some, or all of the received messages. The end station may or may not distinguish between the messages based on the clock source. The end station may validate messages received from a particular clock source.

Abstract: Devices implement encapsulation to support link layer preemption. The device may include a encapsulation logic that encapsulates data, such as an Ethernet frame, to produce an encapsulated frame. The encapsulated frame may include an encapsulation element that indicates whether the encapsulated data includes non-preemptible data, such as Distinguished Minimum Latency Traffic (DMLT), or preemptible data. The encapsulated frame may also indicate whether the encapsulated data comprises the last fragment of a preemptible frame.