Patents by Inventor Eric K. Mann

Eric K. Mann has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10355959
    Abstract: Examples are disclosed for determining or using server transaction latency information. In some examples, a network input/output device coupled to a server may be capable of time stamping information related to ingress request and egress response packets for a transaction. For these examples, elements of the server may be capable of determining transaction latency values based on the time stamped information. The determined transaction latency values may be used to monitor or manage operating characteristics of the server to include an amount of power provided to the server or an ability of the server to support one or more virtual servers. Other examples are described and claimed.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: July 16, 2019
    Assignee: INTEL CORPORATION
    Inventors: Manasi Deval, Jim Daubert, Eric K. Mann, Cong Li, Muralidhar Murali Rajappa, Anjaneya Reddy Chagam Reddy, David Wescott, Ramkumar Nagappan, Raed Kanjo
  • Patent number: 10237171
    Abstract: Methods and apparatus for facilitating efficient Quality of Service (QoS) support for software-based packet processing by offloading QoS rate-limiting to NIC hardware. Software-based packet processing is performed on packet flows received at a compute platform, such as a general purpose server, and/or packet flows generated by local applications running on the compute platform. The packet processing includes packet classification that associates packets with packet flows using flow IDs, and identifying a QoS class for the packet and packet flow. NIC Tx queues are dynamically configured or pre-configured to effect rate limiting for forwarding packets enqueued in the NIC Tx queues. New packet flows are detected, and mapping data is created to map flow IDs associated with flows to the NIC Tx queues used to forward the packets associated with the flows.
    Type: Grant
    Filed: September 20, 2016
    Date of Patent: March 19, 2019
    Assignee: Intel Corporation
    Inventors: Sameh Gobriel, Ren Wang, Eric K. Mann, Christian Maciocco, Tsung-Yuan C. Tai
  • Publication number: 20180083866
    Abstract: Methods and apparatus for facilitating efficient Quality of Service (QoS) support for software-based packet processing by offloading QoS rate-limiting to NIC hardware. Software-based packet processing is performed on packet flows received at a compute platform, such as a general purpose server, and/or packet flows generated by local applications running on the compute platform. The packet processing includes packet classification that associates packets with packet flows using flow IDs, and identifying a QoS class for the packet and packet flow. NIC Tx queues are dynamically configured or pre-configured to effect rate limiting for forwarding packets enqueued in the NIC Tx queues. New packet flows are detected, and mapping data is created to map flow IDs associated with flows to the NIC Tx queues used to forward the packets associated with the flows.
    Type: Application
    Filed: September 20, 2016
    Publication date: March 22, 2018
    Inventors: Sameh Gobriel, Ren Wang, Eric K. Mann, Christian Maciocco, Tsung-Yuan C. Tai
  • Publication number: 20170201448
    Abstract: Examples are disclosed for determining or using server transaction latency information. In some examples, a network input/output device coupled to a server may be capable of time stamping information related to ingress request and egress response packets for a transaction. For these examples, elements of the server may be capable of determining transaction latency values based on the time stamped information. The determined transaction latency values may be used to monitor or manage operating characteristics of the server to include an amount of power provided to the server or an ability of the server to support one or more virtual servers. Other examples are described and claimed.
    Type: Application
    Filed: November 21, 2016
    Publication date: July 13, 2017
    Applicant: INTEL CORPORATION
    Inventors: MANASI DEVAL, JIM DAUBERT, ERIC K. MANN, CONG LI, MURALIDHAR RAJAPPA, ANJANEYA REDDY CHAGAM REDDY, DAVID WESCOTT, RAMKUMAR NAGAPPAN, RAED KANJO
  • Patent number: 9405719
    Abstract: An embodiment may include circuitry that may generate and/or use, at least in part, at least one descriptor to be associated with at least one packet. The at least one descriptor may specify at least one transmission time at which the at least one packet is to be transmitted. The at least one transmission time may be specified in the at least one descriptor in such a manner as to permit the at least one transmission time to be explicitly identified based at least in part upon the at least one descriptor. Many alternatives, modifications, and variations are possible without departing from this embodiment.
    Type: Grant
    Filed: November 11, 2011
    Date of Patent: August 2, 2016
    Assignee: Intel Corporation
    Inventors: Reuven Rozic, Eric K. Mann
  • Patent number: 9372526
    Abstract: A method and system for managing a power state of a processor are described herein. The method includes receiving, at the processor, a signal indicating that an interrupt is to be sent to the processor. The method also includes transitioning the processor from the deep idle state to the shallow idle state in response to receiving the signal and transitioning the processor from the shallow idle state to an active state in response to receiving the interrupt.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: June 21, 2016
    Assignee: Intel Corporation
    Inventors: Devadatta V. Bodas, Eric K. Mann
  • Patent number: 9223379
    Abstract: Methods and systems may provide for determining a plurality of buffer-related settings for a corresponding plurality of idle states and outputting the plurality of buffer-related settings to a device on a platform. The device may determine an observed bandwidth for a channel associated with a receive buffer and identify a selection of a buffer-related setting from the plurality of buffer-related settings based at least in part on the observed bandwidth. In one example, each buffer-related setting includes a latency tolerance and a corresponding idle duration.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: December 29, 2015
    Assignee: Intel Corporation
    Inventors: Eugene Gorbatov, Paul S. Diefenbaugh, Eric K. Mann, Jr-Shian Tsai
  • Publication number: 20140215041
    Abstract: An embodiment may include circuitry to determine at a first hierarchy level of a compute hierarchy, whether to consolidate, at least in part, respective workloads of respective compute entities at the first hierarchy level. The respective workloads may involve one or more respective processes of the respective compute entities. The circuitry may determine whether to consolidate, at least in part, the respective workloads based at least in part upon whether at least one migration condition involving at least one of the one or more respective processes is satisfied. After determining whether to consolidate, at least in part, the respective workloads, the circuitry may determine at a second hierarchy level of the compute hierarchy, whether to consolidate, at least in part, other respective workloads of other respective compute entities at the second hierarchy level. The second hierarchy level may be relatively lower in the compute hierarchy than the first hierarchy level.
    Type: Application
    Filed: March 16, 2012
    Publication date: July 31, 2014
    Inventors: Eric K. Mann, Aviad Wertheimer
  • Publication number: 20140189385
    Abstract: Methods and systems may provide for determining a plurality of buffer-related settings for a corresponding plurality of idle states and outputting the plurality of buffer-related settings to a device on a platform. The device may determine an observed bandwidth for a channel associated with a receive buffer and identify a selection of a buffer-related setting from the plurality of buffer-related settings based at least in part on the observed bandwidth. In one example, each buffer-related setting includes a latency tolerance and a corresponding idle duration.
    Type: Application
    Filed: December 27, 2012
    Publication date: July 3, 2014
    Inventors: Eugene Gorbatov, Paul S. Diefenbaugh, Eric K. Mann, Jr-Shian Tsai
  • Publication number: 20140181555
    Abstract: A method and system for managing a power state of a processor are described herein. The method includes receiving, at the processor, a signal indicating that an interrupt is to be sent to the processor. The method also includes transitioning the processor from the deep idle state to the shallow idle state in response to receiving the signal and transitioning the processor from the shallow idle state to an active state in response to receiving the interrupt.
    Type: Application
    Filed: December 21, 2012
    Publication date: June 26, 2014
    Inventors: Devadatta V. Bodas, Eric K. Mann
  • Patent number: 8661160
    Abstract: In an embodiment, a method is provided. The method of this embodiment provides in response to receiving a packet, determining a packet tuple; generating a hash result by performing a commutative hash function on the packet tuple; and processing the packet on one of a plurality of processors based, at least in part, on the hash result.
    Type: Grant
    Filed: August 30, 2006
    Date of Patent: February 25, 2014
    Assignee: Intel Corporation
    Inventor: Eric K. Mann
  • Publication number: 20130304953
    Abstract: An embodiment may include circuitry that may generate and/or use, at least in part, at least one descriptor to be associated with at least one packet. The at least one descriptor may specify at least one transmission time at which the at least one packet is to be transmitted. The at least one transmission time may be specified in the at least one descriptor in such a manner as to permit the at least one transmission time to be explicitly identified based at least in part upon the at least one descriptor. Many alternatives, modifications, and variations are possible without departing from this embodiment.
    Type: Application
    Filed: November 11, 2011
    Publication date: November 14, 2013
    Inventors: Reuven Rozic, Eric K. Mann
  • Patent number: 8392918
    Abstract: A technique to process interrupts on a virtualized platform. A plurality of virtual machines (VMs) runs on the virtualized platform having at least a processor. The VMs include a power VM. A VM scheduler schedules the VMs for execution on the virtualized platform according a scheduling policy. A virtualized interrupt mask controller controls masking an interrupt from an interrupting source according to the scheduling policy. An interrupt is masked from an interrupting source according to the scheduling policy for at least one of the VMs; and the at least one of the VMs is caused to get the interrupt when the at least one of the VMs is enabled according to the scheduling policy.
    Type: Grant
    Filed: May 13, 2011
    Date of Patent: March 5, 2013
    Assignee: Intel Corporation
    Inventor: Eric K. Mann
  • Patent number: 8295275
    Abstract: An embodiment of the present invention is a technique to tag network transactions. A virtual queue stores packets received from and transmitted to a network interface card (NIC). A global session manager manages packet communication with a capability operating system (COS). A global virtual machine (VM) database stores global session identifiers (SIDs) of the packets and associated metadata. The global SIDs are used by the global session manager to track network sessions. The metadata describe characteristics of session connections. A VM tunnel connection encapsulates the packets passing to and from the COS.
    Type: Grant
    Filed: March 20, 2006
    Date of Patent: October 23, 2012
    Assignee: Intel Corporation
    Inventor: Eric K. Mann
  • Publication number: 20110219374
    Abstract: A technique to process interrupts on a virtualized platform. A plurality of virtual machines (VMs) runs on the virtualized platform having at least a processor. The VMs include a power VM. A VM scheduler schedules the VMs for execution on the virtualized platform according a scheduling policy. A virtualized interrupt mask controller controls masking an interrupt from an interrupting source according to the scheduling policy. An interrupt is masked from an interrupting source according to the scheduling policy for at least one of the VMs; and the at least one of the VMs is caused to get the interrupt when the at least one of the VMs is enabled according to the scheduling policy.
    Type: Application
    Filed: May 13, 2011
    Publication date: September 8, 2011
    Inventor: Eric K. Mann
  • Publication number: 20110208874
    Abstract: A system includes logic to store multiple descriptors, each of the multiple descriptors to be associated with a different set of multiple Transmission Control Protocol/Internet Protocol (TCP/IP) packets received by the network controller, each of the multiple descriptors including a count of the number of packets in the set of multiple packets associated with a respective descriptor. For each of the respective receive packets, the system determines a one of the multiple descriptors based on the network source address, network destination address, source port, and destination port of the respective packet; includes the respective packet in the set of multiple packets associated with the determine one of the multiple descriptors; and updates the one of the multiple descriptors by incrementing the count of the number of packets in the set of multiple packets; and provides data from within the packets to the host.
    Type: Application
    Filed: May 2, 2011
    Publication date: August 25, 2011
    Applicant: Intel Corporation
    Inventors: Eric K. Mann, Patrick L. Connor, Nimrod Diamant
  • Publication number: 20110208871
    Abstract: A system includes a host and a network controller coupled to the host by a bus. The system includes logic to classify Transmission Control Protocol/Internet Protocol (TCP/IP) receive packets based on the network source, network destination, port source, and port destination of the respective receive packets; and cause queuing of the receive packets in a one of multiple receive queues based on the classifying such that receive packets having the same network source, network destination, port source, and port destination are to be queued to the same one of the multiple queues for processing.
    Type: Application
    Filed: May 2, 2011
    Publication date: August 25, 2011
    Applicant: Intel Corporation
    Inventors: Eric K. Mann, Patrick I. Connor, Diamant Nimrod
  • Patent number: 7958506
    Abstract: A technique to process interrupts on a virtualized platform. A plurality of virtual machines (VMs) runs on the virtualized platform having at least a processor. The VMs include a power VM. A VM scheduler schedules the VMs for execution on the virtualized platform according a scheduling policy. A virtualized interrupt mask controller controls masking an interrupt from an interrupting source according to the scheduling policy.
    Type: Grant
    Filed: June 22, 2006
    Date of Patent: June 7, 2011
    Assignee: Intel Corporation
    Inventor: Eric K. Mann
  • Patent number: 7373419
    Abstract: Provided are a method, system, and article of manufacture for managing network throughput. An application identifies at least one network connection of a plurality of network connections, wherein packets arriving via the one network connection require greater resources at a computational device relative to resources required by other network connections. The application determines if resources required at the computational device by the plurality of network connections exceed a threshold and eliminates the at least one network connection to the computational device.
    Type: Grant
    Filed: December 6, 2002
    Date of Patent: May 13, 2008
    Assignee: Intel Corporation
    Inventors: Patrick L. Connor, Eric K. Mann
  • Publication number: 20080077792
    Abstract: In an embodiment, a method is provided. The method of this embodiment provides in response to receiving a packet, determining a packet tuple; generating a hash result by performing a commutative hash function on the packet tuple; and processing the packet on one of a plurality of processors based, at least in part, on the hash result.
    Type: Application
    Filed: August 30, 2006
    Publication date: March 27, 2008
    Inventor: Eric K. Mann