Abstract: Provided is a wireless communication receiver including an antenna for receiving an RF signal; a first mixer, coupled to the antenna, for performing frequency conversion on the RF signal from the antenna by mixing the RF signal with a local oscillator signal to provide a first intermediate frequency (IF) signal; and a first filter, coupled to the first mixer, configured to pass a predetermined band of frequencies of the first IF signal and to generate a first channel signal. The first filter includes a negative feedback loop coupled to the first mixer for performing negative feedback loop control on the first IF signal; and a positive capacitive feedback loop coupled to the first mixer for performing positive capacitive feedback loop control on the first IF signal, the negative feedback loop and the positive capacitive feedback loop being coupled in parallel.

Abstract: Provided is a wireless communication receiver including an antenna for receiving an RF signal; a first mixer, coupled to the antenna, for performing frequency conversion on the RF signal from the antenna by mixing the RF signal with a local oscillator signal to provide a first intermediate frequency (IF) signal; and a first filter, coupled to the first mixer, configured to pass a predetermined band of frequencies of the first IF signal and to generate a first channel signal. The first filter includes a negative feedback loop coupled to the first mixer for performing negative feedback loop control on the first IF signal; and a positive capacitive feedback loop coupled to the first mixer for performing positive capacitive feedback loop control on the first IF signal, the negative feedback loop and the positive capacitive feedback loop being coupled in parallel.

Abstract: A wireless receiver with high linearity, having an out-band signal bypass filter, a mixer, and a baseband circuit. The out-band signal bypass filter has a first terminal and a second terminal respectively receiving a positive differential signal and a negative differential signal from a former-stage circuit, and the out-band signal bypass filter provides an out-band signal bypass path from the first terminal to the second terminal. The mixer receives a filtered signal from the out-band signal bypass filter. The baseband circuit is coupled to the mixer for generation of an in-phase signal and a quadrature phase signal.

Abstract: Third order distortion is reduced in a CMOS transconductor circuit that includes a first N-channel transistor and a first P-channel transistor, gates of the first N-channel transistor and the first P-channel transistor being coupled to receive an input signal. Drains of the first N-channel transistor and first P-channel transistor are coupled to an output conductor. A first degeneration resistor is coupled between a source of the first P-channel transistor and a first supply voltage and a second degeneration resistor is coupled between a source of the first N-channel transistor and a second supply voltage. A first low impedance bypass circuit is coupled between the sources of the first P-channel transistor and the first N-channel transistor.

Abstract: A wireless receiver with high linearity, having an out-band signal bypass filter, a mixer, and a baseband circuit. The out-band signal bypass filter has a first terminal and a second terminal respectively receiving a positive differential signal and a negative differential signal from a former-stage circuit, and the out-band signal bypass filter provides an out-band signal bypass path from the first terminal to the second terminal. The mixer receives a filtered signal from the out-band signal bypass filter. The baseband circuit is coupled to the mixer for generation of an in-phase signal and a quadrature phase signal.

Abstract: Third order distortion is reduced in a CMOS transconductor circuit that includes a first N-channel transistor and a first P-channel transistor, gates of the first N-channel transistor and the first P-channel transistor being coupled to receive an input signal. Drains of the first N-channel transistor and first P-channel transistor are coupled to an output conductor. A first degeneration resistor is coupled between a source of the first P-channel transistor and a first supply voltage and a second degeneration resistor is coupled between a source of the first N-channel transistor and a second supply voltage. A first low impedance bypass circuit is coupled between the sources of the first P-channel transistor and the first N-channel transistor.

Abstract: A sampling phase locked loop (PLL) circuit includes a pull-up/down buffer configured to convert an oscillator reference clock into a square wave sampling control signal input to a sampling phase detector. The buffer circuit is configured to reduce power by controlling the switching of the pull-up and pull-down transistors (and thereby the transitions of the sampling control signal) so that the transistors are not on at the same time.

Abstract: Control circuitry and method of controlling for a sampling phase lock loop (PLL). By controlling the duty cycle of one or more sampling control signals, power consumption by the reference signal buffer and spurious output signals from the sampling PLL being controlled can be reduced.

Abstract: Control circuitry and method of controlling for a sampling phase lock loop (PLL). By controlling the duty cycle of a sampling control signal, in accordance with the PLL reference and output signals, spurious output signals from the sampling PLL being controlled can be reduced.

Abstract: Control circuitry and method of controlling for a sampling phase lock loop (PLL). By controlling the duty cycle of a sampling control signal, in accordance with the PLL reference and output signals, spurious output signals from the sampling PLL being controlled can be reduced.

Abstract: A phase locked loop comprising a phase detector (100) for determining a phase difference between a reference signal (Ref) and mutually phase shifted signals (I, Q) to generate frequency control signals (U, D), the phase detector (100) comprising: means (10) for obtaining a first one of said frequency control signals (U, D) by binary multiplication of the reference signal (Ref) and one of the relative phase shifted signals (I, Q); and means (20) for obtaining a second one of said frequency control signals (U, D) by binary multiplication of the relative phase shifted signals (I, Q).

Abstract: The invention relates to a mixer circuit comprising an input node for receiving an input signal, a first output node 202, and a second output node 203, voltage to current conversion means and switching means operatively coupled to each other and to the input node, the first output node and the second output node to generate a mixed input signal at the first output node and the second output node in response to an oscillator signal. In an embodiment the voltage to current conversion means comprises a first and a second voltage to current converter, implemented as N-MOSFETs M2 and M3, with their gates connected to the input node. The drain of M2 is connected to the first output node 202, while the drain of the M3 is connected to the second output node M3. The source of M2 is connected to the switching node 221, while the source of M3 is connected to the second switching node 222.