Abstract: Methods and apparatus for implementing a Dynamic Voltage Scaling (DVS) system are presented herein. In one embodiment, an embedded delay checker (EDC) cell is used to measure the actual activity and delay of a critical path within a microprocessor core, which is the basis for dynamically altering the voltage to the core. In another embodiment, a slaved ring oscillator (SRO) cell is placed adjacent to the microprocessor core and is used along with EDC cells to provide redundancy to a DVS system.

Abstract: A packet switching architecture provides for a switch system comprised of a cellular base station in communication with the PSTN through a switch. Data packets are routed through the switch system as necessary to effect communication between the public switched telephone network (PSTN) and mobile radiotelephones disposed within the cellular coverage area surrounding the base station. A packet interconnection subsystem operates to transfer data packets between a plurality of interface ports, to which are coupled a corresponding plurality of signal lines. Within the interconnection subsystem, one or more distribution/consolidation (DISCO) interface units are mutually coupled together through a central router unit. Each DISCO interface unit is configured to consolidate the data packets received through at least two signal ports onto a consolidation bus, as well as to distribute the addressed data packets from a distribution bus to two or more of ports.