Abstract: A mixing system for a power washer includes an electrically actuated valve communicated with a supply of a working fluid, and having a valve head that is movable between open and closed positions to control the flow rate of the working fluid through an outlet of the valve. The outlet of the valve is communicated with a fluid passage of the power washer to enable flow of the working fluid into a primary fluid and discharge of a mixture of the primary fluid and working fluid from the power washer when the valve is open, and to provide a flow of primary fluid from the power washer when the valve is closed.

Abstract: A self-checking test generator program creates a self-checking test program that can test a device under test (DUT). The self-checking test generator selects instructions for a test. Selected instructions are executed on a software DUT model to generate results that can be self-checked by other instructions such as compare and branch instructions. The software DUT model has fuzzy models and unknown models for blocks in the DUT. Fuzzy models generate expected outputs for a block of the DUT. Fuzzy models may propagate unknown data from their inputs to their outputs. Unknown models do not predict expected outputs. Instead, unknown models always output unknown (X). Over time, as more of the DUT logic is modeled, unknown models may be replaced with fuzzy models.

Abstract: A simulator simulates and verifies inter-chip functionality in a multi-chip computer system model. The chips within the multi-chip computer system model are characterized by a combination of detailed, low-level hardware models and generalized, high-level hardware emulators. As the simulator executes, inter-chip events are generated which are caused by interactions among and between the hardware models and the hardware emulators. An event processor processes events generated by the simulator, writing events to an event log file. An inter-chip event detector processes the event log file, filtering out inter-chip events caused by the hardware emulators, logging inter-chip events caused by the hardware models. Isolating inter-chip events caused by hardware models helps verification engineers direct the limited number of simulation cycles available during multi-chip verification, thus increasing the confidence level that the multi-chip computer system design is correct.