Abstract: In one example in accordance with the present disclosure, a method includes mapping, using post-package repair, an address associated with a first memory row of a computing device to a spare memory row of the computing device, wherein the spare memory row has a memory failure pattern, and reading data from the spare memory row.

Abstract: A volatile memory device includes a memory array of volatile charge storage cells, a counter to track a time since the volatile memory device has received a read/write command and a control element to automatically change the volatile memory device to a lower power state based on the time tracked by the counter.

Abstract: Example implementations relate to dynamic random-access memory (DRAM) row sparing. In example implementations, utilization of a failed row of a DRAM device may be excluded. A fuse in the DRAM device may be blown to replace the failed row with a spare row. The fuse may be blown during runtime operation of the DRAM device. Error-correcting code (ECC) may be used to correct erroneous data from the failed row while the fuse is being blown. Accesses of the failed row may be redirected to the spare row after the fuse is blown.

Abstract: An example device in accordance with an aspect of the present disclosure includes a memory module having a voltage regulator module (VRM) to receive input power and deliver output power to components of the memory module at a first power plane. A sufficient number of stitching capacitors are to couple the first power plane to a second power plane.

Abstract: A technique includes determining that a row of memory has been activated at a threshold rate. Upon reaching the threshold rate, a refresh rate for the row of memory and an adjacent row of memory may be increased. Subsequent to the increase, the refresh rate may be returned to a default rate.

Abstract: In one example in accordance with the present disclosure, a system for backup of a physical memory region of volatile memory. The system may include: a non-volatile memory, a volatile memory, at least one processor to: execute an application that indicates a virtual memory region stored in the volatile memory, wherein the virtual memory region is associated with an application, determine a corresponding physical memory region of the volatile memory for backup based on the indicated virtual memory region, and at least one memory controller to: receive a backup signal for the physical memory region of the volatile memory, and responsive to receiving the backup signal, backup up the physical memory region of the volatile memory to a memory region of the non-volatile memory.

Abstract: Addresses of memory cells that have errors corrected by error correction operations are evaluated to identify a failed row of memory. Post package repair is implemented on the failed row.

Abstract: An example memory device comprises at least one memory region; and a controller to determine exceeding of a throttling threshold and to throttle processing of access requests for the at least one memory region.

Abstract: Example implementations relate to using a spare memory on a memory module. In example implementations, a memory module may have a plurality of memories, including default memories and a spare memory. A plurality of data buffers on the memory module may select data nibbles from the plurality of memories such that when a default memory is identified as defective, a data nibble is selected from the spare memory and not from the defective default memory. A data nibble selected from the default memory may be in a first position in an output of the memory module when the default memory is functional. A data nibble selected from the spare memory may be in a second position in the output of the memory module.

Abstract: A volatile memory device includes a memory array of volatile charge storage cells, a counter to track a time since the volatile memory device has received a read/write command and a control element to automatically change the volatile memory device to a lower power state based on the time tracked by the counter.

Abstract: A memory device includes a memory storage media to store data for the memory device. A memory manager initiates an autonomous precharge of a buffered page into the memory storage media in the absence of detecting a command at an input of the memory device for a period of time that exceeds a threshold.

Abstract: In one example in accordance with the present disclosure, a method includes mapping, using post-package repair, an address associated with a first memory row of a computing device to a spare memory row of the computing device, wherein the spare memory row has a memory failure pattern, and reading data from the spare memory row.

Abstract: An example device in accordance with an aspect of the present disclosure includes a memory module having a voltage regulator module (VRM) to receive input power and deliver output power to components of the memory module at a first power plane. A sufficient number of stitching capacitors are to couple the first power plane to a second power plane.

Abstract: An example device in accordance with an aspect of the present disclosure includes a memory module having a voltage regulator module (VRM) to receive input power and deliver output power to components of the memory module at a first power plane. At least one stitching capacitor is to couple the first power plane to a second power plane.

Abstract: An example device in accordance with an aspect of the present disclosure includes a memory module having a voltage regulator module (VRM) to receive input power and deliver output power to components of the memory module at a first power plane. At least one stitching capacitor is to couple the first power plane to a second power plane.

Abstract: Example implementations relate to dynamic random-access memory (DRAM) row sparing. In example implementations, utilization of a failed row of a DRAM device may be excluded. A fuse in the DRAM device may be blown to replace the failed row with a spare row. The fuse may be blown during runtime operation of the DRAM device. Error-correcting code (ECC) may be used to correct erroneous data from the failed row while the fuse is being blown. Accesses of the failed row may be redirected to the spare row after the fuse is blown.

Abstract: Examples herein disclose selecting a row of data among multiple rows of data for validation of a repair to the selected row of data. The examples here disclose validating the repair to the selected row of data.

Abstract: A technique includes determining that a row of memory has been activated at a threshold rate. Upon reaching the threshold rate, a refresh rate for the row of memory and an adjacent row of memory may be increased. Subsequent to the increase, the refresh rate may be returned to a default rate.

Abstract: Example implementations relate to using a spare memory on a memory module. In example implementations, a memory module may have a plurality of memories, including default memories and a spare memory. A plurality of data buffers on the memory module may select data nibbles from the plurality of memories such that when a default memory is identified as defective, a data nibble is selected from the spare memory and not from the defective default memory. A data nibble selected from the default memory may be in a first position in an output of the memory module when the default memory is functional. A data nibble selected from the spare memory may be in a second position in the output of the memory module.

Abstract: A technique includes determining, via an analog circuit, where an access rate of a memory row associated with a memory device exceeds a threshold. In various examples, upon a determination that the access rate exceeds the threshold, the technique may further comprise generating an alert to indicate possible corruption of data stored in an adjacent row to the memory row.