Patents by Inventor Eric L. Truebenbach

Eric L. Truebenbach has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6363507
    Abstract: Analog test instrument architecture for performing functional testing of electronic circuit assemblies is disclosed. The analog test instrument includes a plurality of identical channels, each channel including circuitry for driving test stimuli and measuring responses at one node of a circuit assembly under test. The driver and measurement circuitry in each channel implement functions that traditionally have been implemented in a test system using discrete instruments. The analog test instrument further includes a master clock reference, which is used for synchronizing the operation of the driver and measurement circuits. Each channel further includes triggering circuitry for distributing trigger events within the channel and to the other channels; and, an input buffer, which is shared by the measurement circuits in the channel. The synchronized operation, distributed trigger events, and shared input buffers are used to improve the correlation of measurements made during functional testing.
    Type: Grant
    Filed: October 19, 1998
    Date of Patent: March 26, 2002
    Assignee: Teradyne, Inc.
    Inventors: Eric L. Truebenbach, Jiann-Neng Chen, Richard P. Davis, John J. Arena, Teresa P. Lopes, David J. Lind
  • Patent number: 5727021
    Abstract: A printed circuit board tester that compensates for the different propagation length of each channel including a single-input delay cell, at least one multiple-input delay cell, and a multiplexor. The delay cells are connected to one another in a chain. Further, the single-input delay cell is the first delay cell in the chain, and each multiple-input delay cell has the ability to select one of its inputs. A timing signal is applied to each delay cell, and to the multiplexor. The inputs of the multiple-input delay cells are connected to the output of the single-input delay cell, and to the outputs of any preceding multiple-input delay cells in the chain. The single-input delay cell delays the timing signal. Each multiple-input delay cell is programmed by the tester to select one of its inputs; it then delays the selected input. Finally, the multiplexor is programmed by the tester to select either the timing signal or one of the outputs of the delay cells.
    Type: Grant
    Filed: April 3, 1996
    Date of Patent: March 10, 1998
    Assignee: Teradyne, Inc.
    Inventor: Eric L. Truebenbach