Abstract: A system is provided that includes electrodes configured to be implanted in a body, and a pulse generator (PG) circuitry to deliver a stimulus to one or more of the electrodes. The system also includes sensing circuitry configured to define a sensing channel between one or more of the electrodes to sense signals indicative of a physiologic activity of interest, and the sensing circuitry further configured to collect a calibration signal over the sensing channel. The sensing circuitry and PG circuitry are housed within an implantable medical device (IMD). The system also includes one or more processors configured to determine a signal characteristic of interest (COI) of the calibration signal. The one or more processors are also configured to compare a signal COI of the stimulus to the signal COI of the calibration signal, and adjust a parameter of the sensing circuitry or PG circuitry based on the comparison.

Abstract: Example implantable cardiac stimulation devices, pulse generators, and methods providing enhanced cardiac pacing energy are disclosed herein. In an example, an implantable cardiac stimulation device may include a pulse generator having a pacing output node providing cardiac pacing pulses to be applied to a heart of a patient. The pulse generator may include a pulse voltage regulator that receives a pacing signal and generates cardiac pacing pulses at an output of the pulse voltage regulator according to the pacing signal. The pulse voltage regulator may receive a supply voltage to generate cardiac pacing pulses at the supply voltage, gated by the pacing signal.

Abstract: Example implantable cardiac stimulation devices, pulse generators, and methods providing enhanced cardiac pacing energy are disclosed herein. In an example, an implantable cardiac stimulation device may include a pulse generator having a pacing output node providing cardiac pacing pulses to be applied to a heart of a patient. The pulse generator may include a pulse voltage regulator that receives a pacing signal and generates cardiac pacing pulses at an output of the pulse voltage regulator according to the pacing signal. The pulse voltage regulator may receive a supply voltage to generate cardiac pacing pulses at the supply voltage, gated by the pacing signal.

Abstract: The present disclosure provides a cardiac pacing system. The cardiac pacing system includes a right atrial ring electrode, a right atrial tip electrode, a right ventricle ring electrode, and a pacing integrated circuit (IC) including a first pace output node electrically coupled to the right atrial ring electrode, a pace return node electrically coupled to the right atrial tip electrode, and a second pace output node electrically coupled to the right ventricle ring electrode, wherein the pacing IC has a fast discharge configuration that facilitates reducing or eliminating a DC rectification current generated from RF interference during a fast discharge phase.

Abstract: The present disclosure provides a cardiac pacing system. The cardiac pacing system includes a right atrial ring electrode, a right atrial tip electrode, a right ventricle ring electrode, and a pacing integrated circuit (IC) including a first pace output node electrically coupled to the right atrial ring electrode, a pace return node electrically coupled to the right atrial tip electrode, and a second pace output node electrically coupled to the right ventricle ring electrode, wherein the pacing IC has a fast discharge configuration that facilitates reducing or eliminating a DC rectification current generated from RF interference during a fast discharge phase.

Abstract: Described herein are implantable cardiac stimulation devices, and methods for use therewith. A pacing channel of such a device includes a pace output terminal, a pulse generator and at least two pace return electrode terminals. The pace output terminal is coupleable to an electrode for use as an anode. The pulse generator is configured to selectively output an electrical stimulation pulse to the pace output terminal. Each of the pace return electrode terminals is coupleable to a separate one of at least two further electrodes for use as a cathode. Switching circuitry selectively couples any one of the pace return electrode terminals of the pacing channel to the pace return capacitor of the pacing channel at a time, thereby enabling the pace return capacitor to be shared by at least two of the pace return electrode terminals of the pacing channel. Additional embodiments are also disclosed herein.

Abstract: Described herein are implantable cardiac stimulation devices, and methods for use therewith. A pacing channel of such a device includes a pace output terminal, a pulse generator and at least two pace return electrode terminals. The pace output terminal is coupleable to an electrode for use as an anode. The pulse generator is configured to selectively output an electrical stimulation pulse to the pace output terminal. Each of the pace return electrode terminals is coupleable to a separate one of at least two further electrodes for use as a cathode. Switching circuitry selectively couples any one of the pace return electrode terminals of the pacing channel to the pace return capacitor of the pacing channel at a time, thereby enabling the pace return capacitor to be shared by at least two of the pace return electrode terminals of the pacing channel. Additional embodiments are also disclosed herein.

Abstract: A circuit for diminishing mismatch effects between at least two switched signals includes at least three processing circuits configured to receive at least two switched signals such that each of the switched signals is associated with one of the processing circuits leaving at least one unassociated processing circuit. A controller circuit is configured to switch one of the switched signals to be associated with one of the unassociated processing circuit(s) upon at least one specified interval such as, for example, at a transition of the switched signal. The circuit may be incorporated into an audio amplifier configured to provide information carried on the switched signals to one or more speakers that provide an audio output. A one-processor circuit approach includes switching frames of a switched signal between positive and negative inputs of a processor circuit to average out errors introduced by the processor circuit.

Abstract: In accordance with the present invention, there is provided a circuit and method for providing a switchable strong pulldown for a power FET in an off state to avoid inadvertent or false turn ons. A strong pulldown is provided to the gate of a power FET to avoid inadvertent turn on during output swings. In other cases, the gate of the power FET is pulled down weakly to reduce EMI and voltage noise in the circuit. In a particular exemplary embodiment, the present invention provides a circuit and method for obtaining a strong pulldown on the gate of a power FET in an off state, while providing a weak pulldown during turn on to turn off transitions. The invention avoids false turn ons during fast output transitions while maintaining relatively high EMI protection.

Abstract: A system for detecting a direct current (DC) component of a pulse-width modulated (PWM) signal includes a modulator configured to provide at least one PWM signal to an input of an amplifier. A DC detector is configured to detect a DC component of a selected one of the at least one PWM signal as a function of a switching frequency of the selected PWM signal. The DC detector provides at least one report signal that indicates a level of the DC component of the selected PWM signal relative to a predetermined threshold.

Abstract: A circuit for diminishing mismatch effects between at least two switched signals includes at least three processing circuits configured to receive at least two switched signals such that each of the switched signals is associated with one of the processing circuits leaving at least one unassociated processing circuit. A controller circuit is configured to switch one of the switched signals to be associated with one of the unassociated processing circuit(s) upon at least one specified interval such as, for example, at a transition of the switched signal. The circuit may be incorporated into an audio amplifier configured to provide information carried on the switched signals to one or more speakers that provide an audio output. A one-processor circuit approach includes switching frames of a switched signal between positive and negative inputs of a processor circuit to average out errors introduced by the processor circuit.

Abstract: A system for detecting a direct current (DC) component of a pulse-width modulated (PWM) signal includes a modulator configured to provide at least one PWM signal to an input of an amplifier. A DC detector is configured to detect a DC component of a selected one of the at least one PWM signal as a function of a switching frequency of the selected PWM signal. The DC detector provides at least one report signal that indicates a level of the DC component of the selected PWM signal relative to a predetermined threshold.

Abstract: A method of operating a class D amplifier output stage that compensates for nonlinearity introduced by a residual load current during the dead time in the switching of the output stage. The amplifier output stage includes an input, a gate driver circuit, two output transistors, an output, and a current sensing circuit. The transistors are serially connected between the terminals of a power supply. A residual load current flows through the transistors when they are switched off. The gate driver circuit increases or decreases the duty cycles of signals driving the transistors based on the direction of the residual load current flowing through the transistors, thereby causing the duty cycle of the amplifier output to remain substantially constant and equal to the duty cycle of the amplifier input.

Abstract: In accordance with the present invention, there is provided a circuit and method for providing a switchable strong pulldown for a power FET in an off state to avoid inadvertent or false turn ons. A strong pulldown is provided to the gate of a power FET to avoid inadvertent turn on during output swings. In other cases, the gate of the power FET is pulled down weakly to reduce EMI and voltage noise in the circuit. In a particular exemplary embodiment, the present invention provides a circuit and method for obtaining a strong pulldown on the gate of a power FET in an off state, while providing a weak pulldown during turn on to turn off transitions. The invention avoids false turn ons during fast output transitions while maintaining relatively high EMI protection.

Abstract: A method of operating a class D amplifier output stage that compensates for nonlinearity introduced by a residual load current during the dead time in the switching of the output stage. The amplifier output stage includes an input, a gate driver circuit, two output transistors, an output, and a current sensing circuit. The transistors are serially connected between the terminals of a power supply. A residual load current flows through the transistors when they are switched off. The gate driver circuit increases or decreases the duty cycles of signals driving the transistors based on the direction of the residual load current flowing through the transistors, thereby causing the duty cycle of the amplifier output to remain substantially constant and equal to the duty cycle of the amplifier input.

Abstract: A class D amplifier includes an input integrating stage and a modulating stage for modulating the integrated input signal output by the integrating stage. The modulating stage uses as a carrier an alternate waveform of a frequency sufficiently higher than the frequency band of the analog input signal. The modulating stage further outputs a digital signal switching between a positive voltage and a negative voltage, and whose average value represents an amplified replica of the input analog signal. The class D amplifier further includes an output power stage producing an output digital signal. A feedback line including a resistor is connected between the output of the output power stage and an input node of an operational amplifier. The class D amplifier also includes a low-pass filter reconstructing an output analog signal, and a delay stage.