Patents by Inventor Eric Laconde

Eric Laconde has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11437365
    Abstract: A semiconductor substrate of a first conductivity type is coated with a semiconductor layer of a second conductivity type. A buried region of the second conductivity type is formed an interface between the semiconductor substrate and the semiconductor layer. First and second wells of the first conductivity type are provided in the semiconductor layer. A second region of the second conductivity type is formed in the first well. A third region of the second conductivity type is formed in the second well. The first well, the semiconducting layer, the second well and the third region form a first lateral thyristor. The second well, the semiconductor layer, the first well and the second region form a second lateral thyristor. The buried region and semiconductor substrate form a zener diode which sets the trigger voltage for the lateral thyristors.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: September 6, 2022
    Assignee: STMicroelectronics (Tours) SAS
    Inventors: Eric Laconde, Olivier Ory
  • Patent number: 11296071
    Abstract: A device of protection against electrostatic discharges is formed in a semiconductor substrate of a first conductivity type that is coated with a semiconductor layer of a second conductivity type. A buried region of the second conductivity type is positioned at an interface between the semiconductor substrate and the semiconductor layer. First and second wells of the first conductivity type are formed in the semiconductor layer and a region of the second conductivity type is formed in the second well. A stop channel region of the second conductivity type is provided in the semiconductor layer to laterally separating the first well from the second well, where no contact is present between this stop channel region and either of the first and second wells.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: April 5, 2022
    Assignee: STMicroelectronics (Tours) SAS
    Inventors: Eric Laconde, Olivier Ory
  • Publication number: 20200321330
    Abstract: A semiconductor substrate of a first conductivity type is coated with a semiconductor layer of a second conductivity type. A buried region of the second conductivity type is formed an interface between the semiconductor substrate and the semiconductor layer. First and second wells of the first conductivity type are provided in the semiconductor layer. A second region of the second conductivity type is formed in the first well. A third region of the second conductivity type is formed in the second well. The first well, the semiconducting layer, the second well and the third region form a first lateral thyristor. The second well, the semiconductor layer, the first well and the second region form a second lateral thyristor. The buried region and semiconductor substrate form a zener diode which sets the trigger voltage for the lateral thyristors.
    Type: Application
    Filed: March 30, 2020
    Publication date: October 8, 2020
    Applicant: STMicroelectronics (Tours) SAS
    Inventors: Eric LACONDE, Olivier ORY
  • Publication number: 20200321329
    Abstract: A device of protection against electrostatic discharges is formed in a semiconductor substrate of a first conductivity type that is coated with a semiconductor layer of a second conductivity type. A buried region of the second conductivity type is positioned at an interface between the semiconductor substrate and the semiconductor layer. First and second wells of the first conductivity type are formed in the semiconductor layer and a region of the second conductivity type is formed in the second well. A stop channel region of the second conductivity type is provided in the semiconductor layer to laterally separating the first well from the second well, where no contact is present between this stop channel region and either of the first and second wells.
    Type: Application
    Filed: March 30, 2020
    Publication date: October 8, 2020
    Applicant: STMicroelectronics (Tours) SAS
    Inventors: Eric LACONDE, Olivier ORY
  • Patent number: 10643856
    Abstract: Laterally insulated integrated circuit chips are fabricated from a semiconductor wafer. Peripheral trenches are formed in the wafer which laterally delimit integrated circuit chips to be formed. A depth of the peripheral trenches is greater than or equal to a desired final thickness of the integrated circuit chips. The peripheral trenches are formed by a process which repeats successive steps of a) ion etching using a sulfur hexafluoride plasma, and b) passivating using an octafluorocyclobutane plasma. Upon completion of the step of forming the peripheral trenches, lateral walls of the peripheral trenches are covered by an insulating layer of a polyfluoroethene. A thinning step is performed on the lower surface of the wafer until a bottom of the peripheral trenches is reached. The insulating layer is not removed.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: May 5, 2020
    Assignee: STMicroelectronics (Tours) SAS
    Inventors: Mathieu Rouviere, Mohamed Boufnichel, Eric Laconde
  • Publication number: 20190019687
    Abstract: Laterally insulated integrated circuit chips are fabricated from a semiconductor wafer. Peripheral trenches are formed in the wafer which laterally delimit integrated circuit chips to be formed. A depth of the peripheral trenches is greater than or equal to a desired final thickness of the integrated circuit chips. The peripheral trenches are formed by a process which repeats successive steps of a) ion etching using a sulfur hexafluoride plasma, and b) passivating using an octafluorocyclobutane plasma. Upon completion of the step of forming the peripheral trenches, lateral walls of the peripheral trenches are covered by an insulating layer of a polyfluoroethene. A thinning step is performed on the lower surface of the wafer until a bottom of the peripheral trenches is reached. The insulating layer is not removed.
    Type: Application
    Filed: July 12, 2018
    Publication date: January 17, 2019
    Applicant: STMicroelectronics (Tours) SAS
    Inventors: Mathieu ROUVIERE, Mohamed BOUFNICHEL, Eric LACONDE
  • Patent number: 8953290
    Abstract: A device for protecting an integrated circuit against overvoltages, the device being formed inside and on top of a semiconductor substrate of a first conductivity type and including: a capacitor including a well of the second conductivity type penetrating into the substrate and trenches with insulated walls formed in the well and filled with a conductive material; and a zener diode formed by the junction between the substrate and the well.
    Type: Grant
    Filed: July 31, 2013
    Date of Patent: February 10, 2015
    Assignee: STMicroelectronics (Tours) SAS
    Inventors: Olivier Ory, Eric Laconde
  • Publication number: 20140036399
    Abstract: A device for protecting an integrated circuit against overvoltages, the device being formed inside and on top of a semiconductor substrate of a first conductivity type and including: a capacitor including a well of the second conductivity type penetrating into the substrate and trenches with insulated walls formed in the well and filled with a conductive material; and a zener diode formed by the junction between the substrate and the well.
    Type: Application
    Filed: July 31, 2013
    Publication date: February 6, 2014
    Applicant: STMicroelectronics (Tours) SAS
    Inventors: Olivier Ory, Eric Laconde