Patents by Inventor Eric Laconde
Eric Laconde has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240372359Abstract: The present description concerns a device of protection against electrostatic discharges including: at least one first rectifying element including an anode connected to a first terminal and a cathode connected to a first node of the device; at least one second rectifying element including an anode connected to a second node of the device and a cathode connected to the first terminal; and at least one Zener diode or at least one Shockley diode series-connected with a capacitive element between the first and second nodes.Type: ApplicationFiled: April 22, 2024Publication date: November 7, 2024Applicant: STMicroelectronics International N.V.Inventors: Jérôme HEURTIER, Fabrice GUITTON, Eric LACONDE
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Patent number: 11437365Abstract: A semiconductor substrate of a first conductivity type is coated with a semiconductor layer of a second conductivity type. A buried region of the second conductivity type is formed an interface between the semiconductor substrate and the semiconductor layer. First and second wells of the first conductivity type are provided in the semiconductor layer. A second region of the second conductivity type is formed in the first well. A third region of the second conductivity type is formed in the second well. The first well, the semiconducting layer, the second well and the third region form a first lateral thyristor. The second well, the semiconductor layer, the first well and the second region form a second lateral thyristor. The buried region and semiconductor substrate form a zener diode which sets the trigger voltage for the lateral thyristors.Type: GrantFiled: March 30, 2020Date of Patent: September 6, 2022Assignee: STMicroelectronics (Tours) SASInventors: Eric Laconde, Olivier Ory
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Patent number: 11296071Abstract: A device of protection against electrostatic discharges is formed in a semiconductor substrate of a first conductivity type that is coated with a semiconductor layer of a second conductivity type. A buried region of the second conductivity type is positioned at an interface between the semiconductor substrate and the semiconductor layer. First and second wells of the first conductivity type are formed in the semiconductor layer and a region of the second conductivity type is formed in the second well. A stop channel region of the second conductivity type is provided in the semiconductor layer to laterally separating the first well from the second well, where no contact is present between this stop channel region and either of the first and second wells.Type: GrantFiled: March 30, 2020Date of Patent: April 5, 2022Assignee: STMicroelectronics (Tours) SASInventors: Eric Laconde, Olivier Ory
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Publication number: 20200321330Abstract: A semiconductor substrate of a first conductivity type is coated with a semiconductor layer of a second conductivity type. A buried region of the second conductivity type is formed an interface between the semiconductor substrate and the semiconductor layer. First and second wells of the first conductivity type are provided in the semiconductor layer. A second region of the second conductivity type is formed in the first well. A third region of the second conductivity type is formed in the second well. The first well, the semiconducting layer, the second well and the third region form a first lateral thyristor. The second well, the semiconductor layer, the first well and the second region form a second lateral thyristor. The buried region and semiconductor substrate form a zener diode which sets the trigger voltage for the lateral thyristors.Type: ApplicationFiled: March 30, 2020Publication date: October 8, 2020Applicant: STMicroelectronics (Tours) SASInventors: Eric LACONDE, Olivier ORY
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Publication number: 20200321329Abstract: A device of protection against electrostatic discharges is formed in a semiconductor substrate of a first conductivity type that is coated with a semiconductor layer of a second conductivity type. A buried region of the second conductivity type is positioned at an interface between the semiconductor substrate and the semiconductor layer. First and second wells of the first conductivity type are formed in the semiconductor layer and a region of the second conductivity type is formed in the second well. A stop channel region of the second conductivity type is provided in the semiconductor layer to laterally separating the first well from the second well, where no contact is present between this stop channel region and either of the first and second wells.Type: ApplicationFiled: March 30, 2020Publication date: October 8, 2020Applicant: STMicroelectronics (Tours) SASInventors: Eric LACONDE, Olivier ORY
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Patent number: 10643856Abstract: Laterally insulated integrated circuit chips are fabricated from a semiconductor wafer. Peripheral trenches are formed in the wafer which laterally delimit integrated circuit chips to be formed. A depth of the peripheral trenches is greater than or equal to a desired final thickness of the integrated circuit chips. The peripheral trenches are formed by a process which repeats successive steps of a) ion etching using a sulfur hexafluoride plasma, and b) passivating using an octafluorocyclobutane plasma. Upon completion of the step of forming the peripheral trenches, lateral walls of the peripheral trenches are covered by an insulating layer of a polyfluoroethene. A thinning step is performed on the lower surface of the wafer until a bottom of the peripheral trenches is reached. The insulating layer is not removed.Type: GrantFiled: July 12, 2018Date of Patent: May 5, 2020Assignee: STMicroelectronics (Tours) SASInventors: Mathieu Rouviere, Mohamed Boufnichel, Eric Laconde
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Publication number: 20190019687Abstract: Laterally insulated integrated circuit chips are fabricated from a semiconductor wafer. Peripheral trenches are formed in the wafer which laterally delimit integrated circuit chips to be formed. A depth of the peripheral trenches is greater than or equal to a desired final thickness of the integrated circuit chips. The peripheral trenches are formed by a process which repeats successive steps of a) ion etching using a sulfur hexafluoride plasma, and b) passivating using an octafluorocyclobutane plasma. Upon completion of the step of forming the peripheral trenches, lateral walls of the peripheral trenches are covered by an insulating layer of a polyfluoroethene. A thinning step is performed on the lower surface of the wafer until a bottom of the peripheral trenches is reached. The insulating layer is not removed.Type: ApplicationFiled: July 12, 2018Publication date: January 17, 2019Applicant: STMicroelectronics (Tours) SASInventors: Mathieu ROUVIERE, Mohamed BOUFNICHEL, Eric LACONDE
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Patent number: 8953290Abstract: A device for protecting an integrated circuit against overvoltages, the device being formed inside and on top of a semiconductor substrate of a first conductivity type and including: a capacitor including a well of the second conductivity type penetrating into the substrate and trenches with insulated walls formed in the well and filled with a conductive material; and a zener diode formed by the junction between the substrate and the well.Type: GrantFiled: July 31, 2013Date of Patent: February 10, 2015Assignee: STMicroelectronics (Tours) SASInventors: Olivier Ory, Eric Laconde
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Publication number: 20140036399Abstract: A device for protecting an integrated circuit against overvoltages, the device being formed inside and on top of a semiconductor substrate of a first conductivity type and including: a capacitor including a well of the second conductivity type penetrating into the substrate and trenches with insulated walls formed in the well and filled with a conductive material; and a zener diode formed by the junction between the substrate and the well.Type: ApplicationFiled: July 31, 2013Publication date: February 6, 2014Applicant: STMicroelectronics (Tours) SASInventors: Olivier Ory, Eric Laconde