Patents by Inventor Eric Ladizinsky

Eric Ladizinsky has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11930721
    Abstract: Various techniques and apparatus permit fabrication of superconductive circuits. A niobium/aluminum oxide/niobium trilayer may be formed and individual Josephson Junctions (JJs) formed. A protective cap may protect a JJ during fabrication. A hybrid dielectric may be formed. A superconductive integrated circuit may be formed using a subtractive patterning and/or additive patterning. A superconducting metal layer may be deposited by electroplating and/or polished by chemical-mechanical planarization. The thickness of an inner layer dielectric may be controlled by a deposition process. A substrate may include a base of silicon and top layer including aluminum oxide. Depositing of superconducting metal layer may be stopped or paused to allow cooling before completion. Multiple layers may be aligned by patterning an alignment marker in a superconducting metal layer.
    Type: Grant
    Filed: May 8, 2020
    Date of Patent: March 12, 2024
    Assignee: 1372934 B.C. LTD.
    Inventors: Eric Ladizinsky, Jeremy P. Hilton, Byong Hyop Oh, Paul I. Bunyk
  • Patent number: 10991755
    Abstract: Various techniques and apparatus permit fabrication of superconductive circuits and structures, for instance Josephson junctions, which may, for example be useful in quantum computers. For instance, a low magnetic flux noise trilayer structure may be fabricated having a dielectric structure or layer interposed between two elements or layers capable of superconducting. A superconducting via may directly overlie a Josephson junction. A structure, for instance a Josephson junction, may be carried on a planarized dielectric layer. A fin may be employed to remove heat from the structure. A via capable of superconducting may have a width that is less than about 1 micrometer. The structure may be coupled to a resistor, for example by vias and/or a strap connector.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: April 27, 2021
    Assignee: D-WAVE SYSTEMS INC.
    Inventors: Eric Ladizinsky, Geordie Rose, Jeremy P. Hilton, Eugene Dantsker, Byong Hyop Oh
  • Publication number: 20200274050
    Abstract: Various techniques and apparatus permit fabrication of superconductive circuits. A niobium/aluminum oxide/niobium trilayer may be formed and individual Josephson Junctions (JJs) formed. A protective cap may protect a JJ during fabrication. A hybrid dielectric may be formed. A superconductive integrated circuit may be formed using a subtractive patterning and/or additive patterning. A superconducting metal layer may be deposited by electroplating and/or polished by chemical-mechanical planarization. The thickness of an inner layer dielectric may be controlled by a deposition process. A substrate may include a base of silicon and top layer including aluminum oxide. Depositing of superconducting metal layer may be stopped or paused to allow cooling before completion. Multiple layers may be aligned by patterning an alignment marker in a superconducting metal layer.
    Type: Application
    Filed: May 8, 2020
    Publication date: August 27, 2020
    Inventors: Eric Ladizinsky, Jeremy P. Hilton, Byong Hyop Oh, Paul I. Bunyk
  • Patent number: 10700256
    Abstract: Various techniques and apparatus permit fabrication of superconductive circuits. A niobium/aluminum oxide/niobium trilayer may be formed and individual Josephson Junctions (JJs) formed. A protective cap may protect a JJ during fabrication. A hybrid dielectric may be formed. A superconductive integrated circuit may be formed using a subtractive patterning and/or additive patterning. A superconducting metal layer may be deposited by electroplating and/or polished by chemical-mechanical planarization. The thickness of an inner layer dielectric may be controlled by a deposition process. A substrate may include a base of silicon and top layer including aluminum oxide. Depositing of superconducting metal layer may be stopped or paused to allow cooling before completion. Multiple layers may be aligned by patterning an alignment marker in a superconducting metal layer.
    Type: Grant
    Filed: August 17, 2017
    Date of Patent: June 30, 2020
    Assignee: D-WAVE SYSTEMS INC.
    Inventors: Eric Ladizinsky, Jeremy P. Hilton, Byong Hyop Oh, Paul I. Bunyk
  • Publication number: 20200006421
    Abstract: Various techniques and apparatus permit fabrication of superconductive circuits and structures, for instance Josephson junctions, which may, for example be useful in quantum computers. For instance, a low magnetic flux noise trilayer structure may be fabricated having a dielectric structure or layer interposed between two elements or layers capable of superconducting. A superconducting via may directly overlie a Josephson junction. A structure, for instance a Josephson junction, may be carried on a planarized dielectric layer. A fin may be employed to remove heat from the structure. A via capable of superconducting may have a width that is less than about 1 micrometer. The structure may be coupled to a resistor, for example by vias and/or a strap connector.
    Type: Application
    Filed: September 12, 2019
    Publication date: January 2, 2020
    Inventors: Eric Ladizinsky, Geordie Rose, Jeremy P. Hilton, Eugene Dantsker, Byong Hyop Oh
  • Patent number: 10453894
    Abstract: Various techniques and apparatus permit fabrication of superconductive circuits and structures, for instance Josephson junctions, which may, for example be useful in quantum computers. For instance, a low magnetic flux noise trilayer structure may be fabricated having a dielectric structure or layer interposed between two elements or layers capable of superconducting. A superconducting via may directly overlie a Josephson junction. A structure, for instance a Josephson junction, may be carried on a planarized dielectric layer. A fin may be employed to remove heat from the structure. A via capable of superconducting may have a width that is less than about 1 micrometer. The structure may be coupled to a resistor, for example by vias and/or a strap connector.
    Type: Grant
    Filed: April 18, 2018
    Date of Patent: October 22, 2019
    Assignee: D-WAVE SYSTEMS INC.
    Inventors: Eric Ladizinsky, Geordie Rose, Jeremy P. Hilton, Eugene Dantsker, Byong Hyop Oh
  • Publication number: 20180308896
    Abstract: Various techniques and apparatus permit fabrication of superconductive circuits and structures, for instance Josephson junctions, which may, for example be useful in quantum computers. For instance, a low magnetic flux noise trilayer structure may be fabricated having a dielectric structure or layer interposed between two elements or layers capable of superconducting. A superconducting via may directly overlie a Josephson junction. A structure, for instance a Josephson junction, may be carried on a planarized dielectric layer. A fin may be employed to remove heat from the structure. A via capable of superconducting may have a width that is less than about 1 micrometer. The structure may be coupled to a resistor, for example by vias and/or a strap connector.
    Type: Application
    Filed: April 18, 2018
    Publication date: October 25, 2018
    Inventors: Eric Ladizinsky, Geordie Rose, Jeremy P. Hilton, Eugene Dantsker, Byong Hyop Oh
  • Patent number: 9978809
    Abstract: Various techniques and apparatus permit fabrication of superconductive circuits and structures, for instance Josephson junctions, which may, for example be useful in quantum computers. For instance, a low magnetic flux noise trilayer structure may be fabricated having a dielectric structure or layer interposed between two elements or layers capable of superconducting. A superconducting via may directly overlie a Josephson junction. A structure, for instance a Josephson junction, may be carried on a planarized dielectric layer. A fin may be employed to remove heat from the structure. A via capable of superconducting may have a width that is less than about 1 micrometer. The structure may be coupled to a resistor, for example by vias and/or a strap connector.
    Type: Grant
    Filed: October 10, 2016
    Date of Patent: May 22, 2018
    Assignee: D-Wave Systems Inc.
    Inventors: Eric Ladizinsky, Geordie Rose, Jeremy P. Hilton, Eugene Dantsker, Byong Hyop Oh
  • Publication number: 20180033944
    Abstract: Various techniques and apparatus permit fabrication of superconductive circuits. A niobium/aluminum oxide/niobium trilayer may be formed and individual Josephson Junctions (JJs) formed. A protective cap may protect a JJ during fabrication. A hybrid dielectric may be formed. A superconductive integrated circuit may be formed using a subtractive patterning and/or additive patterning. A superconducting metal layer may be deposited by electroplating and/or polished by chemical-mechanical planarization. The thickness of an inner layer dielectric may be controlled by a deposition process. A substrate may include a base of silicon and top layer including aluminum oxide. Depositing of superconducting metal layer may be stopped or paused to allow cooling before completion. Multiple layers may be aligned by patterning an alignment marker in a superconducting metal layer.
    Type: Application
    Filed: August 17, 2017
    Publication date: February 1, 2018
    Inventors: Eric Ladizinsky, Jeremy P. Hilton, Byong Hyop Oh, Paul I. Bunyk
  • Patent number: 9768371
    Abstract: Various techniques and apparatus permit fabrication of superconductive circuits. A niobium/aluminum oxide/niobium trilayer may be formed and individual Josephson Junctions (JJs) formed. A protective cap may protect a JJ during fabrication. A hybrid dielectric may be formed. A superconductive integrated circuit may be formed using a subtractive patterning and/or additive patterning. A superconducting metal layer may be deposited by electroplating and/or polished by chemical-mechanical planarization. The thickness of an inner layer dielectric may be controlled by a deposition process. A substrate may include a base of silicon and top layer including aluminum oxide. Depositing of superconducting metal layer may be stopped or paused to allow cooling before completion. Multiple layers may be aligned by patterning an alignment marker in a superconducting metal layer.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: September 19, 2017
    Assignee: D-Wave Systems Inc.
    Inventors: Eric Ladizinsky, Jeremy P. Hilton, Byong Hyop Oh, Paul I. Bunyk
  • Patent number: 9634224
    Abstract: In one aspect, fabricating a superconductive integrated circuit with a Josephson junction includes applying oxygen or nitrogen to at least part of a structure formed from an outer superconductive layer to passivate an artifact, if any, left from removing the portion of the outer superconductive layer. In another aspect, a first superconductive layer is deposited, a second superconductive layer is deposited on the first superconductive layer, an oxide layer is formed on the first superconductive layer, a dielectric layer is deposited on the oxide layer, a portion of the dielectric layer is removed, a first portion of the oxide layer is removed, a second oxide portion is formed in place of the first portion of the oxide layer, and a third superconductive layer is deposited on the dielectric layer and the second oxide portion.
    Type: Grant
    Filed: January 20, 2015
    Date of Patent: April 25, 2017
    Assignee: D-Wave Systems Inc.
    Inventors: Eric Ladizinsky, Nicolas Ladizinsky, Jason Yao, Byong Hyop Oh, Richard David Neufeld
  • Publication number: 20170098682
    Abstract: Various techniques and apparatus permit fabrication of superconductive circuits and structures, for instance Josephson junctions, which may, for example be useful in quantum computers. For instance, a low magnetic flux noise trilayer structure may be fabricated having a dielectric structure or layer interposed between two elements or layers capable of superconducting. A superconducting via may directly overlie a Josephson junction. A structure, for instance a Josephson junction, may be carried on a planarized dielectric layer. A fin may be employed to remove heat from the structure. A via capable of superconducting may have a width that is less than about 1 micrometer. The structure may be coupled to a resistor, for example by vias and/or a strap connector.
    Type: Application
    Filed: October 10, 2016
    Publication date: April 6, 2017
    Inventors: Eric Ladizinsky, Geordie Rose, Jeremy P. Hilton, Eugene Dantsker, Byong Hyop Oh
  • Patent number: 9490296
    Abstract: Various techniques and apparatus permit fabrication of superconductive circuits and structures, for instance Josephson junctions, which may, for example be useful in quantum computers. For instance, a low magnetic flux noise trilayer structure may be fabricated having a dielectric structure or layer interposed between two elements or layers capable of superconducting. A superconducting via may directly overlie a Josephson junction. A structure, for instance a Josephson junction, may be carried on a planarized dielectric layer. A fin may be employed to remove heat from the structure. A via capable of superconducting may have a width that is less than about 1 micrometer. The structure may be coupled to a resistor, for example by vias and/or a strap connector.
    Type: Grant
    Filed: January 5, 2015
    Date of Patent: November 8, 2016
    Assignee: D-WAVE SYSTEMS INC.
    Inventors: Eric Ladizinsky, Geordie Rose, Jeremy P. Hilton, Eugene Dantsker, Byong Hyop Oh
  • Publication number: 20150236235
    Abstract: In one aspect, fabricating a superconductive integrated circuit with a Josephson junction includes applying oxygen or nitrogen to at least part of a structure formed from an outer superconductive layer to passivate an artifact, if any, left from removing the portion of the outer superconductive layer. In another aspect, a first superconductive layer is deposited, a second superconductive layer is deposited on the first superconductive layer, an oxide layer is formed on the first superconductive layer, a dielectric layer is deposited on the oxide layer, a portion of the dielectric layer is removed, a first portion of the oxide layer is removed, a second oxide portion is formed in place of the first portion of the oxide layer, and a third superconductive layer is deposited on the dielectric layer and the second oxide portion.
    Type: Application
    Filed: January 20, 2015
    Publication date: August 20, 2015
    Inventors: Eric Ladizinsky, Nicolas Ladizinsky, Jason Yao, Byong Hyop Oh, Richard David Neufeld
  • Publication number: 20150187840
    Abstract: Various techniques and apparatus permit fabrication of superconductive circuits and structures, for instance Josephson junctions, which may, for example be useful in quantum computers. For instance, a low magnetic flux noise trilayer structure may be fabricated having a dielectric structure or layer interposed between two elements or layers capable of superconducting. A superconducting via may directly overlie a Josephson junction. A structure, for instance a Josephson junction, may be carried on a planarized dielectric layer. A fin may be employed to remove heat from the structure. A via capable of superconducting may have a width that is less than about 1 micrometer. The structure may be coupled to a resistor, for example by vias and/or a strap connector.
    Type: Application
    Filed: January 5, 2015
    Publication date: July 2, 2015
    Inventors: Eric Ladizinsky, Geordie Rose, Jeremy P. Hilton, Eugene Dantsker, Byong Hyop Oh
  • Publication number: 20150119252
    Abstract: Various techniques and apparatus permit fabrication of superconductive circuits. A niobium/aluminum oxide/niobium trilayer may be formed and individual Josephson Junctions (JJs) formed. A protective cap may protect a JJ during fabrication. A hybrid dielectric may be formed. A superconductive integrated circuit may be formed using a subtractive patterning and/or additive patterning. A superconducting metal layer may be deposited by electroplating and/or polished by chemical-mechanical planarization. The thickness of an inner layer dielectric may be controlled by a deposition process. A substrate may include a base of silicon and top layer including aluminum oxide. Depositing of superconducting metal layer may be stopped or paused to allow cooling before completion. Multiple layers may be aligned by patterning an alignment marker in a superconducting metal layer.
    Type: Application
    Filed: March 7, 2013
    Publication date: April 30, 2015
    Inventors: Eric Ladizinsky, Jeremy P. Hilton, Byong Hyop Oh, Paul I. Bunyk
  • Patent number: 8951808
    Abstract: Various techniques and apparatus permit fabrication of superconductive circuits and structures, for instance Josephson junctions, which may, for example be useful in quantum computers. For instance, a low magnetic flux noise trilayer structure may be fabricated having a dielectric structure or layer interposed between two elements or layers capable of superconducting. A superconducting via may directly overlie a Josephson junction. A structure, for instance a Josephson junction, may be carried on a planarized dielectric layer. A fin may be employed to remove heat from the structure. A via capable of superconducting may have a width that is less than about 1 micrometer. The structure may be coupled to a resistor, for example by vias and/or a strap contact connector.
    Type: Grant
    Filed: February 25, 2010
    Date of Patent: February 10, 2015
    Assignee: D-Wave Systems Inc.
    Inventors: Eric Ladizinsky, Geordie Rose, Jeremy P. Hilton, Eugene Dantsker, Byong Hyop Oh
  • Publication number: 20110089405
    Abstract: Various techniques and apparatus permit fabrication of superconductive circuits and structures, for instance Josephson junctions, which may, for example be useful in quantum computers. For instance, a low magnetic flux noise trilayer structure may be fabricated having a dielectric structure or layer interposed between two elements or layers capable of superconducting. A superconducting via may directly overlie a Josephson junction. A structure, for instance a Josephson junction, may be carried on a planarized dielectric layer. A fin may be employed to remove heat from the structure. A via capable of superconducting may have a width that is less than about 1 micrometer. The structure may be coupled to a resistor, for example by vias and/or a strap connector.
    Type: Application
    Filed: February 25, 2010
    Publication date: April 21, 2011
    Applicant: D-WAVE SYSTEMS INC.
    Inventors: Eric Ladizinsky, Geordie Rose, Jeremy P. Hilton, Eugene Dantsker, Byong Hyop Oh