Abstract: In a method for handling out-of-sequence caller dialog, an intelligent voice interface is configured to lead callers through pathways of an algorithmic dialog that includes available voice prompts for requesting different types of caller information. The method may include, during a voice communication with a caller via a caller device, receiving from the caller device caller input data indicative of a voice input of the caller, without having first provided to the caller device any voice prompt that requests a first type of caller information, and determining, by processing the caller input data, that the voice input includes caller information of the first type. The method also includes after determining that the voice input includes the caller information of the first type, bypassing one or more voice prompts, of the available voice prompts, that request the first type of caller information.

Abstract: A method for facilitating reviews of caller interactions with an intelligent voice interface may include receiving raw voice data representing dialog between one or more callers and the intelligent voice interface during one or more respective voice calls, determining, by processing text translation of the raw voice data using one or more natural language processing models, one or more intents of the one or more callers during the one or more voice calls, generating one or more event labels indicative of one or more events associated with the one or more voice calls, and causing a user interface to be presented on a display device. The user interface may enable a user to (i) listen to the raw voice data, (ii) view the one or more intents, and/or (iii) view the one or more event labels.

Abstract: A multi-port electronic memory has a write through capability. Control features for enabling a write through path to an output and subsequently disabling without causing data errors due to design and technology variations are provided. Control features are especially beneficial for use with compilable SRAM books.

Abstract: A two-port memory cell design which permits simultaneous reading and writing of cells which are on the same wordline but on different Bit Select lines without increase in Read Access Time, and while maintaining memory functionality at low voltages. The memory cell uses a standard 6 transistor design to provide a differential read for fast access plus another three transistors are added to each cell to provide a means of differentially writing the cell and de-gating the write if the bit-select is not active. This cell design has applicability to multi-port memories as well.