Abstract: The invention relates to a method for optimizing the parallel processing of data on a hardware platform, the hardware platform comprising at least one computing unit comprising a plurality of processing units able to execute a plurality of executable tasks in parallel, the data to be processed forming a data set that can be broken down into data subsets, a same sequence of operations being performed on each data subset.

Abstract: The invention relates to a method for optimizing the parallel processing of data on a hardware platform, the hardware platform comprising at least one computing unit comprising a plurality of processing units able to execute a plurality of executable tasks in parallel, the data to be processed forming a data set that can be broken down into data subsets, a same sequence of operations being performed on each data subset.

Abstract: In the field of programmable integrated circuits designed for applications of high-powered computation, a compact system of low complexity is proposed to implement a static schedule scheme for real-time resource management, capable of taking account of the completion of a task.

Abstract: The disclosure relates to a process for simulating a multiprocessor application placed on a target architecture, charactenzed in that it includes at least the following steps:

Abstract: In the field of programmable integrated circuits designed for applications of high-powered computation, a compact system of low complexity is proposed to implement a static schedule scheme for real-time resource management, capable of taking account of the completion of a task.

Abstract: In a multiprocessor machine comprising K channels of different signals, the signals are converted to digital samples by K analog-to-digital converters connected respectively to each channel. N monolithic elementary processors are connected by means of a sample acquisition bus which is common to all of the K analog-to-digital converters. They are also connected by a ring bus which is common to all of the processors so as to permit circulation between processors of the results of computation performed on the samples received by each processor. A control unit and at least one transfer automat synchronized by a common clock signal initiate respectively on the one hand the performance of computations to be carried out by the processors on the samples which they receive as well as on the other hand the transfer of samples on the acquisition bus and the transfer of the results of computation between processors on the ring bus.