Patents by Inventor Eric Leung

Eric Leung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240074013
    Abstract: A lighting fixture appears as a skylight and is referred to as a skylight fixture. First and second light engines of the fixture provide different color points, peak light intensity angles, far-field light distribution characteristics, and/or circadian stimulus values. A skylight fixture may include a sky-resembling assembly and a plurality of sun-resembling assemblies, with dedicated optical assemblies and/or light sources. A lighting fixture may include multiple waveguides that different extraction feature patterns and/or may be sequentially arranged.
    Type: Application
    Filed: August 14, 2023
    Publication date: February 29, 2024
    Inventors: Bernd P. Keller, Michael Leung, Benjamin A. Jacobson, Eric Tarsa, James Ibbetson, Claudio Girotto, Amruteshwar Hiremath
  • Publication number: 20230211110
    Abstract: A heat and moisture exchanger (HME) for engaging a patient’s nose while retrofit into a plenum chamber of a patient interface. The HME includes a frame configured to couple to a ridge of the patient’s nose, and a cradle coupled to the frame. The cradle is configured to be positioned proximate to the patient’s nares. The HME also includes an HME material coupled to the cradle. The HME material is configured to retain moisture exhaled by the patient. Air is configured to pass through the HME material when entering and exiting the patient’s nares. The HME engages and is secured to the patient’s nose independently of any other structure.
    Type: Application
    Filed: July 22, 2021
    Publication date: July 6, 2023
    Inventors: James McKensey BENCKE, Eric LEUNG
  • Publication number: 20170323163
    Abstract: A method is disclosed for interrogating enclosed spaces such as sewers and the like by commanding a camera to travel through the enclosed space while transmitting the video feed from the camera to a remote location for viewing and processing. The processing involves image manipulation before analyzing frames of the video using a neural network developed for this task to identify defects from a library of known defects. Once a new defect is identified, it is inserted into the model to augment the library and improve the accuracy of the program. The operator can pause the process to annotate the images or override the model's determination of the defect for further enhancement of the methodology.
    Type: Application
    Filed: May 5, 2017
    Publication date: November 9, 2017
    Inventor: Kee Eric Leung
  • Patent number: 8769329
    Abstract: A peripheral power management system includes a power monitor for determining a power consumption characteristic of a computing processor and a controller for generating a reference power signal based on the power consumption characteristic. The peripheral power management system also includes a power regulator control signal generator for generating a power regulator control signal based on the reference power signal. The power regulator control signal controls a peripheral device power regulator which regulates an electrical supply power of a peripheral device. In this way, the peripheral power management system controls regulation of the electrical supply power of the peripheral device based on the power consumption characteristic of the computing processor. In some embodiments, the peripheral power management system determines the power consumption characteristic of the computing processor by monitoring communication on a serial voltage identification bus.
    Type: Grant
    Filed: August 19, 2011
    Date of Patent: July 1, 2014
    Assignee: Integrated Device Technology, Inc.
    Inventors: Cheng Wen Hsiao, Eric Leung
  • Patent number: 8732495
    Abstract: Embodiments of the present disclosure include systems, apparatuses, and methods for dynamic frequency and voltage control of components used in a computer system. A system includes a processor voltage regulator and a system clock generator directly operably with each other. The processor voltage regulator provides a core voltage signal to a processor, and is configured to detect a present processor load state of the processor. The system clock generator is for providing a system clock signal to the processor. At least one of the processor voltage regulator or the system clock generator is further configured determine a desired frequency of the system clock signal responsive to the present processor load state, and determine a voltage level for the core voltage signal suitably paired with the desired frequency for proper operation of the processor at the desired frequency. Other systems, apparatuses, and methods are provided.
    Type: Grant
    Filed: August 31, 2010
    Date of Patent: May 20, 2014
    Assignee: Integrated Device Technology, Inc.
    Inventors: Ivan Hsiao, Eric Leung, Frank Matthews, Ordin Kuo, Dinh Bui, Duy Pham, Wallace Ly
  • Publication number: 20120054503
    Abstract: Embodiments of the present disclosure include systems, apparatuses, and methods for dynamic frequency and voltage control of components used in a computer system. A system includes a processor voltage regulator and a system clock generator directly operably with each other. The processor voltage regulator provides a core voltage signal to a processor, and is configured to detect a present processor load state of the processor. The system clock generator is for providing a system clock signal to the processor. At least one of the processor voltage regulator or the system clock generator is further configured determine a desired frequency of the system clock signal responsive to the present processor load state, and determine a voltage level for the core voltage signal suitably paired with the desired frequency for proper operation of the processor at the desired frequency. Other systems, apparatuses, and methods are provided.
    Type: Application
    Filed: August 31, 2010
    Publication date: March 1, 2012
    Applicant: INTEGRATED DEVICE TECHNOLOGY, INC.
    Inventors: Ivan Hsiao, Eric Leung, Frank Matthews, Ordin Kuo, Dinh Bui, Duy Pham, Wallace Ly
  • Patent number: 7815369
    Abstract: A method of measuring temperature of a TMR element includes a step of obtaining in advance a temperature coefficient of element resistance of a discrete TMR element that is not mounted on an apparatus, by measuring temperature versus element resistance value characteristic of the discrete TMR element in a state that a breakdown voltage is intentionally applied to the discrete TMR element and a tunnel barrier layer of the discrete TMR element is brought into a stable conductive state, a step of bringing a tunnel barrier layer of a TMR element actually mounted on the apparatus into a stable conductive state by intentionally applying the breakdown voltage to the mounted TMR element having the same structure as that of the discrete TMR element whose temperature coefficient has been measured, a step of measuring an element resistance value of the mounted TMR element with the tunnel barrier layer that has been brought into a stable conductive state, and a step of obtaining a temperature corresponding to the measure
    Type: Grant
    Filed: February 20, 2008
    Date of Patent: October 19, 2010
    Assignee: TDK Corporation
    Inventors: Yosuke Antoku, Eric Leung, Luke Chung, Man Tse
  • Publication number: 20090207884
    Abstract: A method of measuring temperature of a TMR element includes a step of obtaining in advance a temperature coefficient of element resistance of a discrete TMR element that is not mounted on an apparatus, by measuring temperature versus element resistance value characteristic of the discrete TMR element in a state that a breakdown voltage is intentionally applied to the discrete TMR element and a tunnel barrier layer of the discrete TMR element is brought into a stable conductive state, a step of bringing a tunnel barrier layer of a TMR element actually mounted on the apparatus into a stable conductive state by intentionally applying the breakdown voltage to the mounted TMR element having the same structure as that of the discrete TMR element whose temperature coefficient has been measured, a step of measuring an element resistance value of the mounted TMR element with the tunnel barrier layer that has been brought into a stable conductive state, and a step of obtaining a temperature corresponding to the measure
    Type: Application
    Filed: February 20, 2008
    Publication date: August 20, 2009
    Applicants: TDK CORPORATION, SAE MAGNETICS (H.K.) LTD.
    Inventors: Yosuke ANTOKU, Eric LEUNG, Luke CHUNG, Man TSE
  • Publication number: 20080100288
    Abstract: A seal inspector and a method of inspecting a seal are described. A seal inspector includes an eddy current sensor for detecting changes in an eddy current within a lid seal of a can. The eddy current sensor includes a signal line for creating a magnetic field, which induces the eddy current. The induced eddy current generates a magnetic field that acts on the alternating current and as a consequence produces an eddy current response. A signal processing control unit receives the eddy current response and determines whether a value associated with the eddy current has surpassed a threshold value. If the associated value has surpassed the threshold value, the can may be ejected from a can conveyor system.
    Type: Application
    Filed: October 25, 2006
    Publication date: May 1, 2008
    Applicant: Campbell Soup Company
    Inventors: Eric Leung, Alexander Skulartz, Bob Aguero, Brad K. Menees, Francis Tan, Frank J. Harder, John Knapp, Tom Braydich
  • Publication number: 20070165451
    Abstract: An MRAM circuit includes an MRAM array having a plurality of operational MRAM elements and a reference cell made up of one or more reference MRAM elements. A plurality of program lines within a first region are cladded with a flux-concentrating layer configured to focus a generated magnetic field while the portions of the program lines within a second region are uncladded so that the generated magnetic field is unfocused. Generally, the first region is associated with the operational MRAM elements and the second region is associated with the reference cell.
    Type: Application
    Filed: January 19, 2006
    Publication date: July 19, 2007
    Applicant: Honeywell International Inc.
    Inventor: Eric Leung
  • Publication number: 20060198057
    Abstract: A slider mounted CPP GMR or TMR read head sensor is protected from electrostatic discharge (ESD) damage and from noise and cross-talk from an adjacent write head by means of a balanced resistive/capacitative shunt. The shunt includes highly resistive interconnections between upper and lower shields of the read head and a grounded slider substrate and a low resistance interconnection between the lower pole piece of the write head and the substrate. The capacitances between the pole piece and the upper shield, the upper shield and the lower shield and the lower shield and the substrate are made equal by either forming the shields and pole piece with equal surface areas and separating them with dielectrics of equal thicknesses, or by keeping the ratio of area to insulator thicknesses equal.
    Type: Application
    Filed: March 7, 2005
    Publication date: September 7, 2006
    Inventors: Eric Leung, Anthony Lai, Pak Wong, David Hu, Moris Dovek, Rod Lee
  • Publication number: 20060126224
    Abstract: A thin-film magnetic head that the protrusion of the head end surface due to heat generated from the heating means becomes large enough to set the magnetic spacing dMS to the smaller value efficiently is provided. The head comprises: a substrate having an element-formed surface on which at least one concave portion is formed and an ABS; at least one magnetic head element formed above or on the element-formed surface; at least one thermal expansion layer embedded in the at least one concave portion; and at least one heating means positioned directly above the at least one thermal expansion layer.
    Type: Application
    Filed: November 21, 2005
    Publication date: June 15, 2006
    Applicants: TDK Corporation, SAE Magnetics (H.K.) Ltd.
    Inventors: Takamitsu Sakamoto, Taro Oike, Katsuki Kurihara, Eric Leung