Abstract: A method for localization and generation of short critical sequence uses an automatic test equipment to test an electronic device (e.g., memory device) by circuit simulation to localize and re-generate a very short critical sequence from a set of long worst-case pattern. The method includes defining a failure mechanism condition for search and localization process and re-production of the short critical sequence based on a mutation process from the critical sequence detected from a step (I) phase and number of pattern defined in population using a genetic algorithm step (II) phase.

Abstract: The invention relates to a design analysis technique for a test pattern analysis of chips via automatic test equipment (ATE) or a circuit simulation to detect potential design weakness or abnormal behavior in real customer application faults. Problems are solved by comprising a simulation procedure stored in an LRT database of automatic test equipment (ATE), defining test conditions and test patterns which execute and generate continuously for a time given by a user, applying the test stimuli and test conditions to a device under test (DUT) and starting the long running test (LRT), stopping the test automatically if any application faults occur and logging the failure time and timely test sequence and starting another test again until a given maximum number of tests are reached.