Abstract: An electronic package having multiple pins may be tested in parallel for output short circuit current by simulating a direct short to ground by simultaneously connecting multiple output pins directly to ground in order to active a current limiter associated with each of the output pins. The pins are then connected to a resistive connection to ground via a set of resistors; the direct ground is then removed, such that the current limiter associated with each of the output pins remains activated. A voltage drop across each of the set of resistors is measured simultaneously. An output short circuit current fault is indicated when the voltage drop across any of the resistors exceeds a threshold value corresponding to a maximum output short circuit current value.

Abstract: An electronic package having multiple pins may be tested in parallel for output short circuit current by simulating a direct short to ground by simultaneously connecting multiple output pins directly to ground in order to active a current limiter associated with each of the output pins. The pins are then connected to a resistive connection to ground via a set of resistors; the direct ground is then removed, such that the current limiter associated with each of the output pins remains activated. A voltage drop across each of the set of resistors is measured simultaneously.

Abstract: An integrated circuit (IC) with an oscillator and electrostatic discharge (ESD) protection in which the parasitic capacitance of the ESD protection circuitry is disassociated from the oscillator circuitry to minimize loading of the tank circuit thereby minimizing degradation of the tank circuit quality factor (Q).