Abstract: Embodiments described herein may include apparatus, systems, techniques, and/or processes that are directed to optimizing memory frequency based on the bandwidth and latency needs of heterogeneous processing cores in a computer system. According to various embodiments, adjustments to the frequency of memory may be applied differently depending on the type of core requesting more bandwidth and/or faster response. According to various embodiments, the frequency is increased more sparingly for energy-efficient cores, while the frequency is increased more generously for high-performance cores. Additionally, when memory traffic decreases, the frequency of memory is decreased more generously when the previous request for higher frequency was from an energy-efficient core than a high-performance core. By considering the type of core that is requesting more bandwidth and/or faster response, performance and power consumption may be more optimally balanced.

Abstract: Critically representative features (CRF's) for use in mask-making verification and/or resist development verification are defined and/or copied into the in-scribe area used by wafer CD features. The placement of mask-CRF's in the wafer CD bar region eliminates the problem of correctly and quickly locating mask-CRF's at different positions in the in-die areas of a manufactured mask. On-wafer counterparts of the mask-CRF's may be used for fine-tuning lithography and patterning processes.

Abstract: Critically representative features (CRF's) for use in mask-making verification and/or resist development verification are defined and/or copied into the in-scribe area used by wafer CD features. The placement of mask-CRF's in the wafer CD bar region eliminates the problem of correctly and quickly locating mask-CRF's at different positions in the in-die areas of a manufactured mask. On-wafer counterparts of the mask-CRF's may be used for fine-tuning lithography and patterning processes.

Abstract: A photoresist exposure process is disclosed which produces features which are substantially smaller than the aperture dimension of the mask used to make the feature. The smaller feature size results from a double exposure of the photoresist, combined with a double baking process to create the features in the photoresist. The double baking process thins the layer of photoresist, prior to the second exposure, thereby improving the resolution of the mark created by the second exposure on the photoresist. The process also uses a binary bias mask through which the first exposure is made, which overlaps with the area of the second exposure, to allow a process tolerance for the realignment of the mask over the wafer for the second exposure.

Abstract: A photoresist exposure process is disclosed which produces features which are substantially smaller than the aperture dimension of the mask used to make the feature. The smaller feature size results from a double exposure of the photoresist, combined with a double baking process to create the features in the photoresist. The double baking process thins the layer of photoresist, prior to the second exposure, thereby improving the resolution of the mark created by the second exposure on the photoresist. The process also uses a binary bias mask through which the first exposure is made, which overlaps with the area of the second exposure, to allow a process tolerance for the realignment of the mask over the wafer for the second exposure.