Patents by Inventor Eric LUM
Eric LUM has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230077847Abstract: Compositions and methods for controlling pests are provided. The methods involve transforming organisms with a nucleic acid sequence encoding an insecticidal protein. In particular, the nucleic acid sequences are useful for preparing plants and microorganisms that possess insecticidal activity. Thus, transformed bacteria, plants, plant cells, plant tissues and seeds are provided. Compositions are insecticidal nucleic acids and proteins of bacterial species. The sequences find use in the construction of expression vectors for subsequent transformation into organisms of interest including plants, as probes for the isolation of other homologous (or partially homologous) genes. The pesticidal proteins find use in controlling, inhibiting growth or killing Lepidopteran, Coleopteran, Dipteran, fungal, Hemipteran and nematode pest populations and for producing compositions with insecticidal activity.Type: ApplicationFiled: October 25, 2022Publication date: March 16, 2023Inventors: Lu LIU, Amy LUM, Azalea S. ONG, Eric SCHEPERS, Ingrid UDRANSZKY, Xiaohong ZHONG
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Patent number: 11525144Abstract: Compositions and methods for controlling pests are provided. The methods involve transforming organisms with a nucleic acid sequence encoding an insecticidal protein. In particular, the nucleic acid sequences are useful for preparing plants and microorganisms that possess insecticidal activity. Thus, transformed bacteria, plants, plant cells, plant tissues and seeds are provided. Compositions are insecticidal nucleic acids and proteins of bacterial species. The sequences find use in the construction of expression vectors for subsequent transformation into organisms of interest including plants, as probes for the isolation of other homologous (or partially homologous) genes. The pesticidal proteins find use in controlling, inhibiting growth or killing Lepidopteran, Coleopteran, Dipteran, fungal, Hemipteran and nematode pest populations and for producing compositions with insecticidal activity.Type: GrantFiled: March 12, 2019Date of Patent: December 13, 2022Assignees: PIONEER HI-BRED INTERNATIONAL, INC., HEXIMA LIMITEDInventors: Lu Liu, Amy Lum, Azalea S. Ong, Eric Schepers, Ingrid Udranszky, Xiaohong Zhong
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Patent number: 10713756Abstract: One aspect of the current disclosure provides a method of upscaling an image. The method includes: rendering an image, wherein the rendering includes generating color samples of the image at a first resolution and depth samples of the image at a second resolution, which is higher than the first resolution; and upscaling the image to an upscaled image at a third resolution, which is higher than the first resolution, using the color samples and the depth samples.Type: GrantFiled: May 1, 2018Date of Patent: July 14, 2020Assignee: Nvidia CorporationInventors: Rouslan Dimitrov, Lei Yang, Chris Amsinck, Walter Donovan, Eric Lum, Rui Bastos
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Publication number: 20190340730Abstract: One aspect of the current disclosure provides a method of upscaling an image. The method includes: rendering an image, wherein the rendering includes generating color samples of the image at a first resolution and depth samples of the image at a second resolution, which is higher than the first resolution; and upscaling the image to an upscaled image at a third resolution, which is higher than the first resolution, using the color samples and the depth samples.Type: ApplicationFiled: May 1, 2018Publication date: November 7, 2019Inventors: Rouslan Dimitrov, Lei Yang, Chris Amsinck, Walter Donovan, Eric Lum, Rui Bastos
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Patent number: 10453168Abstract: A tile coalescer within a graphics processing pipeline coalesces coverage data into tiles. The coverage data indicates, for a set of XY positions, whether a graphics primitive covers those XY positions. The tile indicates, for a larger set of XY positions, whether one or more graphics primitives cover those XY positions. The tile coalescer includes coverage data in the tile only once for each XY position, thereby allowing the API ordering of the graphics primitives covering each XY position to be preserved. The tile is then distributed to a set of streaming multiprocessors for shading and blending operations. The different streaming multiprocessors execute thread groups to process the tile. In doing so, those thread groups may perform read-modify-write operations with data stored in memory. Each such thread group is scheduled to execute via atomic operations, and according to the API order of the associated graphics primitives.Type: GrantFiled: August 17, 2018Date of Patent: October 22, 2019Assignee: NVIDIA CORPORATIONInventors: Ziyad Hakura, Eric Lum, Dale Kirkland, Jack Choquette, Patrick R. Brown, Yury Y. Uralsky, Jeffrey Bolz
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Publication number: 20180374185Abstract: A tile coalescer within a graphics processing pipeline coalesces coverage data into tiles. The coverage data indicates, for a set of XY positions, whether a graphics primitive covers those XY positions. The tile indicates, for a larger set of XY positions, whether one or more graphics primitives cover those XY positions. The tile coalescer includes coverage data in the tile only once for each XY position, thereby allowing the API ordering of the graphics primitives covering each XY position to be preserved. The tile is then distributed to a set of streaming multiprocessors for shading and blending operations. The different streaming multiprocessors execute thread groups to process the tile. In doing so, those thread groups may perform read-modify-write operations with data stored in memory. Each such thread group is scheduled to execute via atomic operations, and according to the API order of the associated graphics primitives.Type: ApplicationFiled: August 17, 2018Publication date: December 27, 2018Inventors: Ziyad Hakura, Eric Lum, Dale Kirkland, Jack Choquette, Patrick R. Brown, Yury Y. Uralsky, Jeffrey Bolz
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Patent number: 10055806Abstract: A tile coalescer within a graphics processing pipeline coalesces coverage data into tiles. The coverage data indicates, for a set of XY positions, whether a graphics primitive covers those XY positions. The tile indicates, for a larger set of XY positions, whether one or more graphics primitives cover those XY positions. The tile coalescer includes coverage data in the tile only once for each XY position, thereby allowing the API ordering of the graphics primitives covering each XY position to be preserved. The tile is then distributed to a set of streaming multiprocessors for shading and blending operations. The different streaming multiprocessors execute thread groups to process the tile. In doing so, those thread groups may perform read-modify-write operations with data stored in memory. Each such thread group is scheduled to execute via atomic operations, and according to the API order of the associated graphics primitives.Type: GrantFiled: October 27, 2015Date of Patent: August 21, 2018Assignee: NVIDIA CORPORATIONInventors: Ziyad Hakura, Eric Lum, Dale Kirkland, Jack Choquette, Patrick R. Brown, Yury Y. Uralsky, Jeffrey Bolz
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Patent number: 10032245Abstract: A tile coalescer within a graphics processing pipeline coalesces coverage data into tiles. The coverage data indicates, for a set of XY positions, whether a graphics primitive covers those XY positions. The tile indicates, for a larger set of XY positions, whether one or more graphics primitives cover those XY positions. The tile coalescer includes coverage data in the tile only once for each XY position, thereby allowing the API ordering of the graphics primitives covering each XY position to be preserved. The tile is then distributed to a set of streaming multiprocessors for shading and blending operations. The different streaming multiprocessors execute thread groups to process the tile. In doing so, those thread groups may perform read-modify-write operations with data stored in memory. Each such thread group is scheduled to execute via atomic operations, and according to the API order of the associated graphics primitives.Type: GrantFiled: October 27, 2015Date of Patent: July 24, 2018Assignee: NVIDIA CORPORATIONInventors: Ziyad Hakura, Eric Lum, Dale Kirkland, Jack Choquette, Patrick R. Brown, Yury Y. Uralsky, Jeffrey Bolz
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Patent number: 10019776Abstract: A tile coalescer within a graphics processing pipeline coalesces coverage data into tiles. The coverage data indicates, for a set of XY positions, whether a graphics primitive covers those XY positions. The tile indicates, for a larger set of XY positions, whether one or more graphics primitives cover those XY positions. The tile coalescer includes coverage data in the tile only once for each XY position, thereby allowing the API ordering of the graphics primitives covering each XY position to be preserved. The tile is then distributed to a set of streaming multiprocessors for shading and blending operations. The different streaming multiprocessors execute thread groups to process the tile. In doing so, those thread groups may perform read-modify-write operations with data stored in memory. Each such thread group is scheduled to execute via atomic operations, and according to the API order of the associated graphics primitives.Type: GrantFiled: October 27, 2015Date of Patent: July 10, 2018Assignee: NVIDIA CORPORATIONInventors: Ziyad Hakura, Eric Lum, Dale Kirkland, Jack Choquette, Patrick R. Brown, Yury Y. Uralsky, Jeffrey Bolz
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Publication number: 20170116698Abstract: A tile coalescer within a graphics processing pipeline coalesces coverage data into tiles. The coverage data indicates, for a set of XY positions, whether a graphics primitive covers those XY positions. The tile indicates, for a larger set of XY positions, whether one or more graphics primitives cover those XY positions. The tile coalescer includes coverage data in the tile only once for each XY position, thereby allowing the API ordering of the graphics primitives covering each XY position to be preserved. The tile is then distributed to a set of streaming multiprocessors for shading and blending operations. The different streaming multiprocessors execute thread groups to process the tile. In doing so, those thread groups may perform read-modify-write operations with data stored in memory. Each such thread group is scheduled to execute via atomic operations, and according to the API order of the associated graphics primitives.Type: ApplicationFiled: October 27, 2015Publication date: April 27, 2017Inventors: ZIYAD HAKURA, ERIC LUM, DALE KIRKLAND, JACK CHOQUETTE, PATRICK R. BROWN, YURY Y. URALSKY, JEFFREY BOLZ
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Publication number: 20170116700Abstract: A tile coalescer within a graphics processing pipeline coalesces coverage data into tiles. The coverage data indicates, for a set of XY positions, whether a graphics primitive covers those XY positions. The tile indicates, for a larger set of XY positions, whether one or more graphics primitives cover those XY positions. The tile coalescer includes coverage data in the tile only once for each XY position, thereby allowing the API ordering of the graphics primitives covering each XY position to be preserved. The tile is then distributed to a set of streaming multiprocessors for shading and blending operations. The different streaming multiprocessors execute thread groups to process the tile. In doing so, those thread groups may perform read-modify-write operations with data stored in memory. Each such thread group is scheduled to execute via atomic operations, and according to the API order of the associated graphics primitives.Type: ApplicationFiled: October 27, 2015Publication date: April 27, 2017Inventors: ZIYAD HAKURA, ERIC LUM, DALE KIRKLAND, JACK CHOQUETTE, PATRICK R. BROWN, YURY Y. URALSKY, JEFFREY BOLZ
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Publication number: 20170116699Abstract: A tile coalescer within a graphics processing pipeline coalesces coverage data into tiles. The coverage data indicates, for a set of XY positions, whether a graphics primitive covers those XY positions. The tile indicates, for a larger set of XY positions, whether one or more graphics primitives cover those XY positions. The tile coalescer includes coverage data in the tile only once for each XY position, thereby allowing the API ordering of the graphics primitives covering each XY position to be preserved. The tile is then distributed to a set of streaming multiprocessors for shading and blending operations. The different streaming multiprocessors execute thread groups to process the tile. In doing so, those thread groups may perform read-modify-write operations with data stored in memory. Each such thread group is scheduled to execute via atomic operations, and according to the API order of the associated graphics primitives.Type: ApplicationFiled: October 27, 2015Publication date: April 27, 2017Inventors: ZIYAD HAKURA, ERIC LUM, DALE KIRKLAND, JACK CHOQUETTE, PATRICK R. BROWN, YURY Y. URALSKY, JEFFREY BOLZ
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Patent number: 9633458Abstract: In a graphics processing pipeline, a processing unit establishes a bounding box around a polygon in order to identify sample points that are covered by the polygon. For a given sample point included within the bounding box, the processing unit constructs a set of lines that intersect at the sample point, where each line in the set of lines is parallel to at least one side of the polygon. When all vertices of the polygon reside on one side of at least one line in the set of lines, the processing unit may reduce the size of the bounding box to exclude the sample point.Type: GrantFiled: January 23, 2012Date of Patent: April 25, 2017Assignee: NVIDIA CorporationInventors: Walter R. Steiner, Eric Lum, Dale L. Kirkland, Steven James Heinrich, David Charles Patrick
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Patent number: 9495781Abstract: A technique for early sample evaluation during coarse rasterization of primitives reduces the number of pixel tiles that are processed during fine rasterization of the primitive. A primitive bounding box determines when a primitive is small and may not actually cover any samples within at least one fine raster tile. Early sample evaluation is performed for the small primitive during coarse rasterization and the small primitive is discarded when no samples are actually covered by the small primitive. When the small primitive lies on a boundary between at least two fine raster tiles, early sample evaluation is performed during coarse rasterization to correctly identify which, if any, of the at least two fine raster tiles includes samples that are actually covered by the small primitive.Type: GrantFiled: June 21, 2012Date of Patent: November 15, 2016Assignee: NVIDIA CorporationInventors: Eric Lum, Walter R. Steiner, Justin Cobb
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Patent number: 9495721Abstract: Techniques for dispatching pixel information in a graphics processing pipeline. A fragment processing unit generates a pixel that includes multiple samples based on a first portion of a graphics primitive received by a first thread. The fragment processing unit calculates a first value for the first pixel, where the first value is calculated only once for the pixel. The fragment processing unit calculates a first set of values for the samples, where each value in the first set of values corresponds to a different sample and is calculated only once for the corresponding sample. The fragment processing unit combines the first value with each value in the first set of values to create a second set of values. The fragment processing unit creates one or more dispatch messages to store the second set of values in a set of output registers.Type: GrantFiled: December 21, 2012Date of Patent: November 15, 2016Assignee: NVIDIA CorporationInventors: Jerome F. Duluk, Jr., Rouslan Dimitrov, Eric Lum, Rui Bastos
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Patent number: 9367946Abstract: A computing system and method for representing volumetric data for a scene. One embodiment of the computing system includes: (1) a memory configured to store a three-dimensional (3D) clipmap data structure having at least one clip level and at least one mip level, and (2) a processor configured to generate voxelized data for a scene and cause the voxelized data to be stored in the 3D clipmap data structure.Type: GrantFiled: January 24, 2014Date of Patent: June 14, 2016Assignee: NVIDIA CORPORATIONInventors: Alexey Panteleev, Yury Uralsky, Evgeny Makarov, Henry Moreton, Sergey Bolotov, Eric Lum, Alexey Barkovoy, Cyril Crassin
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Publication number: 20150242988Abstract: A method for reducing redundant rendering of frames includes receiving draw calls including state information for a frame. The method includes generating respective bounding boxes for the draw calls. The bounding box is generated based on vertex data, vertex programs and transformation matrices. The method includes comparing the draw calls of the frame to the draw calls of one or more previous frames and identifying draw calls that are not identical in the compared frames. The method includes identifying the bounding boxes containing altered regions of the frames based on the draw calls that are not identical in the compared frames. The method includes reducing the altered regions into a smaller set of clip rectangles and rendering only inside the clip rectangles.Type: ApplicationFiled: February 20, 2015Publication date: August 27, 2015Inventors: Jeffrey Bolz, Xinheng Li, Eric Lum, Emmett Kilgariff
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Publication number: 20150109298Abstract: A computing system and method for representing volumetric data for a scene. One embodiment of the computing system includes: (1) a memory configured to store a three-dimensional (3D) clipmap data structure having at least one clip level and at least one mip level, and (2) a processor configured to generate voxelized data for a scene and cause the voxelized data to be stored in the 3D clipmap data structure.Type: ApplicationFiled: January 24, 2014Publication date: April 23, 2015Applicant: Nvidia CorporationInventors: Alexey Panteleev, Yury Uralsky, Evgeny Makarov, Henry Moreton, Sergey Bolotov, Eric Lum, Alexey Barkovoy, Cyril Crassin
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Publication number: 20140176579Abstract: Techniques are disclosed for dispatching pixel information in a graphics processing pipeline. A fragment processing unit generates a pixel that includes multiple samples based on a first portion of a graphics primitive received by a first thread. The fragment processing unit calculates a first value for the first pixel, where the first value is calculated only once for the pixel. The fragment processing unit calculates a first set of values for the samples, where each value in the first set of values corresponds to a different sample and is calculated only once for the corresponding sample. The fragment processing unit combines the first value with each value in the first set of values to create a second set of values. The fragment processing unit creates one or more dispatch messages to store the second set of values in a set of output registers. One advantage of the disclosed techniques is that pixel shader programs perform per-sample operations with increased efficiency.Type: ApplicationFiled: December 21, 2012Publication date: June 26, 2014Applicant: NVIDIA CORPORATIONInventors: Jerome F. Duluk, JR., Rouslan DIMITROV, Eric LUM, Rui BASTOS
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Publication number: 20130342547Abstract: A technique for early sample evaluation during coarse rasterization of primitives reduces the number of pixel tiles that are processed during fine rasterization of the primitive. A primitive bounding box determines when a primitive is small and may not actually cover any samples within at least one fine raster tile. Early sample evaluation is performed for the small primitive during coarse rasterization and the small primitive is discarded when no samples are actually covered by the small primitive. When the small primitive lies on a boundary between at least two fine raster tiles, early sample evaluation is performed during coarse rasterization to correctly identify which, if any, of the at least two fine raster tiles includes samples that are actually covered by the small primitive.Type: ApplicationFiled: June 21, 2012Publication date: December 26, 2013Inventors: Eric LUM, Walter R. STEINER, Justin COBB