Abstract: Solder bumps are formed on a substrate, such as a semiconductor die (28) or wafer, using a screen printing and reflow operation. Solder paste (18) is screened into openings (14) of a stencil (10). The paste is reflowed within the stencil to produce a solder preform (22). The stencil and solder preforms are then aligned over the substrate to be bumped so that the preform aligns with a metal pad (30) on the substrate. The solder preforms are again reflowed, and the solder within the openings of the stencil is drawn onto the metal pad. To facilitate the transfer of the solder from the stencil to the metal pad, a second stencil (12) can be used to form a protrusion (27) on the solder preform. The protrusion contacts the metal pad during the transfer reflow operation to facilitate removing the solder from the stencil.

Abstract: Probing array bumped semiconductor devices using cantilever probe needles is facilitated by the formation of peripheral test pads. A semiconductor die (10) includes bond pads (12). A redistribution metallization layer is deposited and patterned to form individual redistribution structures (26) associated with and electrically coupled to each bond pad. Each redistribution structure includes a test pad (28), a bump pad (30) and a bump pad interconnect (32). The test pads are formed in positions close to those of the underlying bond pads, while the bump pads can be formed anywhere within the die. Having the test pads located similarly to the bond pads enables the same or a similar probe card apparatus and cantilever needles (50) to probe the die either at the bond pads for devices which are to be wire bonded or TAB bonded, or at the test pads for devices which are to be bumped.

Abstract: A method for forming conductive bumps (60, 62) on a semiconductor device (50) using a mask structure (20) employs two masks (22, 24) individually fabricated and positioned in a back-to-back relationship. Each mask is patterned and isotropically etched to form a plurality of tapered openings (30, 40) corresponding to a pattern of terminal pads (54) on the semiconductor device. Metal is evaporated through the openings and onto the terminal pads. The mask structure is removed and the remaining metal is reflowed to form the conductive bumps. Using a mask structure having two individual masks (each with a thickness of one-half a typical mask thickness) enables smaller openings to be etched in each mask. Upon joining the two masks, the effective aspect ratio of the mask structure is reduced to produce smaller and denser conductive bumps without loss of volume and height control.

Abstract: A method, and product created thereby, by which low melting point solder suitable for reflow connection of components is formed on select contacts of a printed circuit board. The method is particularly suited to the fabrication of populated printed circuit board having fine pitch devices including flip-chip devices, connected on a board including conventional coarse pitch surface mounted components. The fine pitch contacts of the board are exposed through holes in a stencil characterized in its ability to withstand solder reflow temperatures, not be wettable by solder, and have a coefficient of thermal expansion relatively matching the printed circuit board. Low temperature solder paste is screen deposited into the stencil openings. With the stencil fixedly positioned on the board, the solder paste retained by the stencil pattern is reflowed to selectively form on the underlying contacts of the printed circuit board.

Abstract: A contactor structure employed in a high speed electronic test system for testing the electrical integrity of the conductive paths (or lines) in the packaging substrate prior to the mounting and connection thereto of the high circuit density monolithic devices. The contactor structure includes a semiconductor space transformer fabricated by large scale integration techniques and containing a plurality of discrete first integrated circuits. The first integrated circuits of the space transformer being respectively electrically connected to said electrical probes. Second integrated circuitry interconnecting said first integrated circuits is also contained within said semiconductor space transformer. Under control of said test system said second integrated circuitry selectively energizes, selected first and second ones of said first integrated circuits.