Patents by Inventor Eric M. Panning

Eric M. Panning has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8865376
    Abstract: Methods are provided for fabricating a process structure, such as a mask or mask blank. The methods include, for instance: providing a silicon substrate; forming a multi-layer, extreme ultra-violet lithography (EUVL) structure over the silicon substrate; subsequent to forming the multi-layer EUVL structure over the crystalline substrate, reducing a thickness of the silicon substrate; and attaching a low-thermal-expansion material (LTEM) substrate to one of the multi-layer EUVL structure, or the reduced silicon substrate. In one implementation, the silicon substrate is a silicon wafer with a substantially defect-free surface upon which the multi-layer EUVL structure is formed. The multi-layer EUVL structure may include multiple bi-layers of a first material and a second material, as well as a capping layer, and optionally, an absorber layer, where the absorber layer is patternable to facilitating forming a EUVL mask from the process structure.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: October 21, 2014
    Assignees: Sematech, Inc., Intel Corporation
    Inventors: Vibhu Jindal, Frank Goodwin, Patrick A. Kearney, Eric M. Panning
  • Publication number: 20140255828
    Abstract: Methods are provided for fabricating a process structure, such as a mask or mask blank. The methods include, for instance: providing a silicon substrate; forming a multi-layer, extreme ultra-violet lithography (EUVL) structure over the silicon substrate; subsequent to forming the multi-layer EUVL structure over the crystalline substrate, reducing a thickness of the silicon substrate; and attaching a low-thermal-expansion material (LTEM) substrate to one of the multi-layer EUVL structure, or the reduced silicon substrate. In one implementation, the silicon substrate is a silicon wafer with a substantially defect-free surface upon which the multi-layer EUVL structure is formed. The multi-layer EUVL structure may include multiple bi-layers of a first material and a second material, as well as a capping layer, and optionally, an absorber layer, where the absorber layer is patternable to facilitating forming a EUVL mask from the process structure.
    Type: Application
    Filed: March 8, 2013
    Publication date: September 11, 2014
    Applicants: INTEL CORPORATION, SEMATECH, INC.
    Inventors: Vibhu JINDAL, Frank GOODWIN, Patrick A. KEARNEY, Eric M. PANNING
  • Publication number: 20080073592
    Abstract: A reflective optical illumination collector is described. In one example, the collector has a ring to collect light from a light source within a range of incident angles and to reflect the light off an inner surface of the ring to a target image of the collector. A plurality of rings concentric to the first ring may also be used. Each ring collects light from the light source within a range of incident angles and reflects the light off an inner surface of the respective ring to the target image of the collector.
    Type: Application
    Filed: July 21, 2006
    Publication date: March 27, 2008
    Inventors: Eric M. Panning, Michael Goldstein, Ranju D. Venables
  • Patent number: 7316893
    Abstract: Modular containment cell arrangements, including modular containment cells to contain an item and at least one processing material associated with processing of the item.
    Type: Grant
    Filed: November 18, 2002
    Date of Patent: January 8, 2008
    Assignee: Intel Corporation
    Inventors: Eric M. Panning, Hok-kin Choi
  • Patent number: 7208747
    Abstract: According to an embodiment of the invention, an adjustable EUV light source may be used for photolithography. The EUV light source, such as an electrode, is mounted in an adjustable housing. The housing can be adjusted to change the distance between the light source and focusing mirrors, which in turn changes the partial coherence value of the system. The partial coherence value can be changed to print different types of semiconductor features.
    Type: Grant
    Filed: May 12, 2006
    Date of Patent: April 24, 2007
    Assignee: Intel Corporation
    Inventors: Manish Chandhok, Eric M. Panning, Bryan J. Rice
  • Patent number: 7098466
    Abstract: According to an embodiment of the invention, an adjustable EUV light source may be used for photolithography. The EUV light source, such as an electrode, is mounted in an adjustable housing. The housing can be adjusted to change the distance between the light source and focusing mirrors, which in turn changes the partial coherence value of the system. The partial coherence value can be changed to print different types of semiconductor features.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: August 29, 2006
    Assignee: Intel Corporation
    Inventors: Manish Chandhok, Eric M. Panning, Bryan J. Rice
  • Publication number: 20040106048
    Abstract: Modular containment cell arrangements, including modular containment cells to contain an item and at least one processing material associated with processing of the item.
    Type: Application
    Filed: November 18, 2002
    Publication date: June 3, 2004
    Inventors: Eric M. Panning, Hok-Kin Choi