Abstract: A drilling fluid conditioning system for a well system includes a return conduit configured to receive drilling fluid recirculated from a wellbore of the well system, a drilling fluid pre-chilling system in fluid communication with and downstream from the return conduit, wherein the drilling fluid pre-chilling system includes a cooler configured to transfer heat from the drilling fluid to a heat sink, a solids separator in fluid communication with and upstream from the cooler, and a fluid powered jet pump for pumping the drilling fluid from the solids separator to the cooler of the drilling fluid pre-chilling system, a solids control system in fluid communication with and downstream from the drilling fluid pre-chilling system, wherein the solids control system is configured to separate at least some solids from the drilling fluid.

Abstract: A memory controller includes a command queue with multiple entry stacks, each with a plurality of entries holding memory access commands, one or more parameter indicators each holding a respective characteristic common to the plurality of entries, and a head indicator designating a current entry for arbitration. An arbiter has a single command input for each entry stack. A command queue loader circuit receives incoming memory access commands and loads entries of respective entry stacks with memory access commands having the respective characteristic of each of the one or more parameter indicators in common.

Abstract: A method for controlling a data processing system includes detecting a droop in a power supply voltage of a functional circuit of the data processing system greater than a programmable droop threshold. An operation of the data processing system is throttled according to a programmable step size, a programmable assertion time, and a programmable de-assertion time in response to detecting the droop.

Abstract: A method for performing read training of a memory channel includes writing a data pattern to a memory using a data bus having a predetermined number of bit lanes. An edge of a read data eye is determined individually for each bit lane by reading the data pattern over the data bus using a read bust cycle having a predetermined length, grouping data received on each bit lane over the read burst cycle to form a bit lane data group, and comparing the bit lane data group to corresponding expected data of the data pattern for each bit lane, logging a phase of each bit lane on which said edge is found, and repeating the reading, grouping, comparing, and logging until the edge is found for all of the bit lanes.

Abstract: A method for controlling a data processing system includes detecting a droop in a power supply voltage of a functional circuit of the data processing system greater than a programmable droop threshold. An operation of the data processing system is throttled according to a programmable step size, a programmable assertion time, and a programmable de-assertion time in response to detecting the droop.

Abstract: A method for performing read training of a memory channel includes writing a data pattern to a memory using a data bus having a predetermined number of bit lanes. An edge of a read data eye is determined individually for each bit lane by reading the data pattern over the data bus using a read bust cycle having a predetermined length, grouping data received on each bit lane over the read burst cycle to form a bit lane data group, and comparing the bit lane data group to corresponding expected data of the data pattern for each bit lane, logging a phase of each bit lane on which said edge is found, and repeating the reading, grouping, comparing, and logging until the edge is found for all of the bit lanes.

Abstract: A memory controller includes a command queue with multiple entry stacks, each with a plurality of entries holding memory access commands, one or more parameter indicators each holding a respective characteristic common to the plurality of entries, and a head indicator designating a current entry for arbitration. An arbiter has a single command input for each entry stack. A command queue loader circuit receives incoming memory access commands and loads entries of respective entry stacks with memory access commands having the respective characteristic of each of the one or more parameter indicators in common.

Abstract: An impeller is positioned within the flow of a fluid to be used to irrigate an area. The impeller drives a generator, which operates to charge and sustain a storage battery. The battery powers a receiver having an identification code by which the receiver may be addressed to receive commands, such as, for example, to open or close a valve, thereby providing fluid to irrigate an area. By opening the valve, the fluid flow is increased, and more power is generated and stored in the battery. In this way, power is generated automatically for the receiver, which, in turn, controls the fluid flow for irrigation.