Abstract: An integrated demodulator tuning circuit (10, 60) receives differential currents at input terminals (12, 46) and provides an AFC signal at an output terminal (48). The AFC current characteristic has a dead band (72) in the output current generated when the integrated demodulator tuning circuit (10, 60) operates under the condition where the difference between the currents supplied at the input terminals (12 and 46) is at or below a set threshold value. The set threshold value is determined by the relative sizes of the transistors (14, 16 and 20, 36, 38 and 40) that form the current mirrors connected to the input terminals (12, 46).

Abstract: A demodulator circuit (10) having harmonic cancelling receives an input signal (IF) and generates an oscillator signal (OSC) in an oscillator circuit (14). The oscillator signal (OSC) is locked to the same frequency and phase as the input signal (IF). A phase shift circuit (18) generates a shifted signal (OSC SHIFTED) that is in quadrature with the oscillator signal (OSC). A multiplier (22) receives the oscillator signal (OSC) and the shifted signal (OSC SHIFTED) and generates an output signal (2IF) having twice the frequency of the oscillator signal (OSC). A multiplier circuit (24) also receives the input signal (IF) and along with the oscillator signal (OSC) generates an output signal (PD). The signals generated by the multiplier (22) and the multiplier circuit (24) are summed in a summing circuit (30) that supplies an output signal (OUT).

Abstract: A demodulator circuit (10) having harmonic cancelling receives an input signal (IF) and generates an oscillator signal (OSC) in an oscillator circuit (14). The oscillator signal (OSC) is locked to the same frequency and phase as the input signal (IF). A phase shift circuit (18) generates a shifted signal (OSC SHIFTED) that is in quadrature with the oscillator signal (OSC). A multiplier (22) receives the oscillator signal (OSC) and the shifted signal (OSC SHIFTED) and generates an output signal (21F) having twice the frequency of the oscillator signal (OSC). A multiplier circuit (24) also receives the input signal (IF) and along with the oscillator signal (OSC) generates an output signal (PD). The signals generated by the multiplier (22) and the multiplier circuit (24) are summed in a summing circuit (30) that supplies an output signal (OUT).

Abstract: An integrated demodulator tuning circuit (10, 60) receives differential currents at input terminals (12, 46) and provides an AFC signal at an output terminal (48). The AFC current characteristic has a dead band (72) in the output current generated when the integrated demodulator tuning circuit (10, 60) operates under the condition where the difference between the currents supplied at the input terminals (12 and 46) is at or below a set threshold value. The set threshold value is determined by the relative sizes of the transistors (14, 16 and 20, 36, 38 and 40) that form the current mirrors connected to the input terminals (12, 46).

Abstract: A demodulator circuit (10) includes an oscillator (12) and an injection circuit (14). An Automatic Frequency Control (AFC) signal adjusts the tail current of a current source (28) provided in the oscillator (12) and the tail current of a current source (44) provided in the injection circuit (14). A phase detector (16) compares the phase of the signal generated by the oscillator (12) with the phase of the injected input signal. The phase detector (16) generates an output signal V0 having a value of zero when the input signal is in quadrature with the signal generated by the oscillator (12), but generates a non-zero signal that is used to adjust the AFC signal when the input signal and the signal generated by the oscillator (12) are not in quadrature.

Abstract: A circuit for doubling the frequency of an input signal. The circuit includes a full-wave rectifier that rectifies the input signal to generate an output signal with double the frequency of the input signal. The output signal is compared to a predetermined voltage. Based on this comparison, a control signal is fed back to the full-wave rectifier and the output of the rectifier is adjusted to a predetermined level. In this manner the frequency of the input signal is doubled, and the output power is maintained constant, independent of the input power level.

Abstract: An RF buffer (10) supplies a single ended output signal and differential output signals. An average voltage of the differential output signals is compared to a reference voltage (VR) by an amplifier (40). The amplifier (40) provides a feedback signal for controlling the bias current conducted by a first transistor (24) and a mirrored bias current conducted by a second transistor (46). The bias currents conducted by the first and second transistors (24, 46) are used to generate the differential output signals (OUT-, OUT+) and are substantially independent of the signal level at an input terminal (20). The signal current conducted by the first transistor (24) controls an output transistor (66), while the signal current conducted by the second transistor (46) controls another output transistor (56) in the push-pull output stage of the RF buffer (10).

Abstract: A linear differential gain stage (31) has a first input (32), a second input (33), a first output (34), and a second output (35). A differential input voltage is coupled to an input differential transistor pair (39,40). Voltage compensation circuits (53,54) cancel non-linearities due to the input differential transistor pair (39,40). Parasitic capacitance of the input differential transistor pair (39,40) couple current to the first and second inputs (32,33) due to voltage transitions at the first and second outputs (34,35). The current to the first and second inputs (32,33) is canceled by impedance compensation circuits (55,56) that provide an equal magnitude but opposite sign current. The result is an almost infinite input impedance to the linear differential gain stage (31).

Abstract: A current mirror circuit (31) that includes an active loop which operates transistors of different conductivity type at equal base-emitter junction voltages to minimize error. A first resistor (38) couples to a base of a first transistor (32) of a first conductivity type in a voltage follower configuration. A reference current is coupled to the first resistor (38). The voltage across the first resistor (38) and base-emitter junction of the first transistor (32) is mirrored across the base-emitter junction of a second transistor (34) of a second conductivity type and a second resistor (39). A third transistor (35) of the second conductivity type in a diode configuration is coupled to receive current from the second transistor (34). The voltage across the third transistor (35) biases a fourth transistor (33) of a first conductivity type. The current from the fourth transistor (33) is provided to the first transistor such that the first and second transistors (32,34) operate at equal base-emitter voltages.

Abstract: A demodulator circuit (100) and method for producing a demodulated signal V.sub.OUT from an input signal V.sub.IN. A frequency detection circuit (101) produces a quadrature signal V.sub.QUAD which is compared to the input signal V.sub.IN to produce a detected output signal. The phase and frequency of the quadrature signal V.sub.QUAD are responsive to a control signal I.sub.CONTROL. The demodulator circuit (100) has an output terminal (114) which provides the demodulated signal V.sub.OUT. Nonlinearity in the demodulated output signal V.sub.OUT in relation to a modulating signal is reduced by a linearizing feedback circuit (102). Automatic tuning is provided by a tuning feedback circuit (103). The output signals produced at the respective output terminals (114) and (113) of the linearizing feedback circuit (102) and tuning feedback circuit (103) are summed to produce the control current I.sub.CONTROL.

Abstract: A amplifier (21) having increased linearity, low input impedance, and low noise is provided. The amplifier (21) has an input (22), a bias input, a first output (23), and a second output (33). A first transistor (26) has a collector coupled to the first output (23), a base coupled to the bias input, and an emitter. A first resistor (27) is coupled between the emitter of the first transistor (26) and the input (22). A second transistor (29) has a collector and base coupled in common, and an emitter coupled for receiving a power supply voltage. A second resistor (28) couples between the input (22) and the common base and collector of the second transistor (29). A third transistor (32) has a collector coupled to the second output (33), a base coupled to the common base and collector of the second transistor (29), and an emitter coupled for receiving the power supply voltage. An input signal applied to the input (22) generates a differential current at the first and second outputs (23, 33).

Abstract: A demodulation circuit (10) performs quadrature demodulation on an IF input signal. The IF input signal processes through a preamplifier (12) to one input of a mixer (14). The mixer output goes to first and second multipliers (20, 22). A VCO (24) generates an oscillator signal that processes through a first multiplier (26) and first and second dividers (28, 30) to generate in-phase and quadrature recovered carrier signals that are applied to second inputs of the first and second multipliers which in turn produce the in-phase and quadrature demodulated baseband signals. A switching arrangement (32, 38, 40) for the multiplier and dividers provides the proper frequency signal to a second input of the mixer to generate sum and difference frequencies. A filter and amplifier at the output of the mixer removes the summation frequency leaving the difference frequency to the first and second multipliers.

Abstract: A data slicer including a comparator and a clamping circuit has been provided wherein the clamping circuit functions to clamp a signal appearing at a first input of the comparator to a predetermined voltage swing. The first input of the comparator is coupled through a capacitive element to receive an input signal. The clamping circuit includes a first diode being coupled between the first input of the comparator and a first voltage. The clamping circuit also includes a transistor having its current carrying electrodes coupled between a first supply voltage terminal and the first input of the comparator. The control electrode of the transistor is coupled to receive a second voltage. The second input of the comparator is coupled to receive a bias voltage which is substantially equal to the midpoint of the first and second voltages. The data slicer further includes a hold circuit for disabling the clamping circuit.

Abstract: A current mirror provides an output current that is scaled in magnitude with respect to an applied input current includes first and second current turnaround circuits and circuitry coupled between the two current turnaround circuits which is responsive to the first current turnaround circuit for sourcing a current to the second current turnaround circuit the magnitude of which is scaled with respect to the input current that is sourced to the first current turn around circuit.

Abstract: A variable gain control circuit comprising an input stage and an output stage is responsive to an applied input signal for providing an output signal. The input stage and output stage are independently biased by respective bias sources and each include circuitry responsive to a dynamic control voltage, the latter of which is generated in response to the input signal, to permit the absolute magnitudes of the input signal and output signal to exceed the respective bias sources. The ratio of the output and input signals is proportional to the ratio of the bias sources.

Abstract: A circuit for producing output pulses in response to an alternating signal supplied to the input thereof which is comprised of a pair of complementary transistors cascoded between a pair of current mirror circuits which source and sink currents to and from a common terminal respectively. The alternating input signal is applied to the interconnected emitters of the two transistors thereby rendering one more conductive while the other is rendered less conductive and vice versa. The currents which are sourced or sunk at the common terminal are proportional to the currents flowing in the two transistors and are compared to cause an output transistor to switch operating states thereby producing the output pulse.

Abstract: An active differential load circuit which receives a differential input signal applied to first and second inputs thereof and produces a single ended output signal at an output thereof while unwanted higher frequency signals applied thereto are filtered from the output without ground currents. The load includes a pair of transistors which have, in the preferred embodiment, their collectors connected together via series connected first and second resistors with the interconnection between the two resistors being connected to the bases of the two transistors. The collectors are also respectively coupled to a pair of current sources and the respective emitters receiving the applied differential input signal. A filter capacitor is coupled between the collectors of the two transistors and efffectively shorts the unwanted higher frequency signals thereacross.

Abstract: A variable reactance, the value of which is controllable, is produced between a pair of terminals of a variable reactance circuit comprising a pair of current steering circuits. First and second reactive components are coupled respectively between the pair of terminals and the first and second current steering circuits to produce first and second antiphase reactive currents'. The first reactive current is split by the first current steering circuit into first and second antiphased proportional currents. Likewise, the second reactive current is split by the second current steering circuit into third and fourth antiphased proportional currents with said first and third currents being antiphased with respect to each other. The first reactive current is summed at a first one of the pair of terminals with said first and third currents while the second reactive current is summed at the second one of the pair of terminals with said second and fourth currents to produce the variable reactance across the terminals.

Abstract: A balanced LC oscillator for providing differential oscillator output signals includes a pair of transistors the emitters of which are connected to a voltage reference source that provides a fixed voltage thereto. The base electrodes of each transistor is cross coupled to the collector of the other transistor. The LC tank circuit is connected between the collectors of the two transistors and current supply is provided thereto. Although the potential at the bases of the two transistors vary with respect to the oscillator signal appearing thereat, the emitters are held at a fixed potential to eliminate any common mode signal that may otherwise be generated if the potential at the emitters was permitted to vary.

Abstract: A circuit for driving a serial data bus with serial logic data that is supplied to the circuit while buffering the logic data supplying circuit from the data bus. The circuit provides logic output pulses having controlled slew rates wherein the input logic data is not distorted but which inhibits undesired high frequency components associated with the fast rise and fall times of the leading and trailing edges of the input logic data pulses. The circuit comprises an inverting amplifier having capacitive feedback between the output and the inverting input of the amplifier, a buffer amplifier between the output of the inverting amplifier and the output of the circuit, and current switching circuitry for sinking and sourcing currents of equal magnitude at the input of the inverting amplifier depending on the relative magnitude of the input logic data pulses.