Patents by Inventor Eric Mann

Eric Mann has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240081708
    Abstract: Embodiments disclosed herein are directed to a self-learning bladder volume monitoring system. The system can include a bladder volume (BV) system configured to measure an electrical impedance of a bladder region of a patient and determine a volume of fluid disposed therein using an impedance to bladder volume model (“By model”). Further, the system can measure a total body water (“TBW”) for the patient and modify the BV model to account for variations in TBW within the tissues surrounding the bladder providing a more accurate bladder volume measurement. The system can include a “training unit” which can include one of a user input interface, an automatic urine output monitoring system, an ultrasound system, and an intrabladder pressure system configured to verify a volume of fluid within or voided from the bladder and train the BV model.
    Type: Application
    Filed: February 23, 2022
    Publication date: March 14, 2024
    Inventors: Timothy J. Kelly, Eric A. Fallows, Robert Cancelosi, Damien Marechal, Yolanda Rhodes, Gregory Mann, Alexandra A. Falis
  • Patent number: 11770109
    Abstract: An integrated circuit can include an amplifier coupled to receive an analog input signal, an anti-aliasing filter (AAF) coupled to an output of the amplifier, a buffer circuit coupled to an output of the AAF, a sigma-delta modulator configured to generate a digital data stream in response to an output of the buffer, and a plurality of chopping circuits nested within one another, including a first pair of chopping circuits having at least the amplifier disposed therebetween and configured to remove offset in the analog input signal, and a second pair of chopping circuit having at least the first pair of chopping circuits disposed therebetween. The amplifier, AAF, sigma-delta modulator, and chopping circuits can be formed with the same integrated circuit substrate. Corresponding methods and systems are also disclosed.
    Type: Grant
    Filed: September 1, 2022
    Date of Patent: September 26, 2023
    Assignee: Cypress Semiconductor Corporation
    Inventors: Erhan Hancioglu, Eashwar Thiagarajan, Eric Mann, Harold Kutz, Vaibhav Ramamoorthy, Rajiv Singh, Amsby Richardson, Jr.
  • Publication number: 20230055860
    Abstract: An integrated circuit can include an amplifier coupled to receive an analog input signal, an anti-aliasing filter (AAF) coupled to an output of the amplifier, a buffer circuit coupled to an output of the AAF, a sigma-delta modulator configured to generate a digital data stream in response to an output of the buffer, and a plurality of chopping circuits nested within one another, including a first pair of chopping circuits having at least the amplifier disposed therebetween and configured to remove offset in the analog input signal, and a second pair of chopping circuit having at least the first pair of chopping circuits disposed therebetween. The amplifier, AAF, sigma-delta modulator, and chopping circuits can be formed with the same integrated circuit substrate. Corresponding methods and systems are also disclosed.
    Type: Application
    Filed: September 1, 2022
    Publication date: February 23, 2023
    Applicant: Cypress Semiconductor Corporation
    Inventors: Erhan Hancioglu, Eashwar Thiagarajan, Eric Mann, Harold Kutz, Vaibhav Ramamoorthy, Rajiv Singh, Amsby Richardson, JR.
  • Patent number: 11502952
    Abstract: Devices and techniques for reorder resilient transport are described herein. A device may store data packets in sequential positions of a flow queue in an order in which the data packets were received. The device may retrieve a first data packet from a first sequential position and a second data packet from a second sequential position that is next in sequence to the first sequential position in the flow queue. The device may store the first data packet and the second data packet in a buffer and refrain from providing the first data packet and the second data packet to upper layer circuitry if the packet order information for the first data packet and the second data packet indicate that the first data packet and the second data packet were received out of order. Other embodiments are also described.
    Type: Grant
    Filed: May 2, 2018
    Date of Patent: November 15, 2022
    Assignee: Intel Corporation
    Inventors: Anil Vasudevan, Parthasarathy Sarangam, Eric Mann, Daniel Cohn
  • Patent number: 11437961
    Abstract: An integrated circuit can include an amplifier coupled to receive an analog input signal, an anti-aliasing filter (AAF) coupled to an output of the amplifier, a buffer circuit coupled to an output of the AAF, a sigma-delta modulator configured to generate a digital data stream in response to an output of the buffer, and a plurality of chopping circuits nested within one another, including a first pair of chopping circuits having at least the amplifier disposed therebetween and configured to remove offset in the analog input signal, and a second pair of chopping circuit having at least the first pair of chopping circuits disposed therebetween. The amplifier, AAF, sigma-delta modulator, and chopping circuits can be formed with the same integrated circuit substrate. Corresponding methods and systems are also disclosed.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: September 6, 2022
    Assignee: Cypress Semiconductor Corporation
    Inventors: Erhan Hancioglu, Eashwar Thiagarajan, Eric Mann, Harold Kutz, Vaibhav Ramamoorthy, Rajiv Singh, Amsby Richardson, Jr.
  • Patent number: 11416466
    Abstract: Disclosed are system and methods for processing and storing data files, using a data edge file format. The data edge file separates information about what symbols are in a data file and information about the corresponding location of those symbols in the data file. The described technique for converting a source file comprising symbols into a data edge file includes: generating a locality file of symbol location from the source file to identify locations of the symbols in the source file, generating a symbol file to identify symbols in the source file, and then modifying the locality file of symbol location to associate each symbol from the symbol file with a location in the source file.
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: August 16, 2022
    Assignee: CHAOSSEARCH, INC.
    Inventors: Thomas Hazel, David Noblet, Eric Mann, Grant Mills
  • Patent number: 11386063
    Abstract: Disclosed are system and methods for processing and storing data files, using a data edge file format. The data edge file separates information about what symbols are in a data file and information about the corresponding location of those symbols in the data file. The described technique for converting a source file comprising symbols into a data edge file includes: generating a locality file of symbol location from the source file to identify locations of the symbols in the source file, generating a symbol file to identify symbols in the source file, and then modifying the locality file of symbol location to associate each symbol from the symbol file with a location in the source file.
    Type: Grant
    Filed: May 20, 2021
    Date of Patent: July 12, 2022
    Assignee: CHAOSSEARCH, INC.
    Inventors: Thomas Hazel, David Noblet, Eric Mann, Grant Mills
  • Publication number: 20210408986
    Abstract: An integrated circuit can include an amplifier coupled to receive an analog input signal, an anti-aliasing filter (AAF) coupled to an output of the amplifier, a buffer circuit coupled to an output of the AAF, a sigma-delta modulator configured to generate a digital data stream in response to an output of the buffer, and a plurality of chopping circuits nested within one another, including a first pair of chopping circuits having at least the amplifier disposed therebetween and configured to remove offset in the analog input signal, and a second pair of chopping circuit having at least the first pair of chopping circuits disposed therebetween. The amplifier, AAF, sigma-delta modulator, and chopping circuits can be formed with the same integrated circuit substrate. Corresponding methods and systems are also disclosed.
    Type: Application
    Filed: June 26, 2020
    Publication date: December 30, 2021
    Applicant: Cypress Semiconductor Corporation
    Inventors: Erhan Hancioglu, Eashwar Thiagarajan, Eric Mann, Harold Kutz, Vaibhav Ramamoorthy, Rajiv Singh, Amsby Richardson, JR.
  • Publication number: 20210271658
    Abstract: Disclosed are system and methods for processing and storing data files, using a data edge file format. The data edge file separates information about what symbols are in a data file and information about the corresponding location of those symbols in the data file. The described technique for converting a source file comprising symbols into a data edge file includes: generating a locality file of symbol location from the source file to identify locations of the symbols in the source file, generating a symbol file to identify symbols in the source file, and then modifying the locality file of symbol location to associate each symbol from the symbol file with a location in the source file.
    Type: Application
    Filed: May 20, 2021
    Publication date: September 2, 2021
    Inventors: Thomas HAZEL, David NOBLET, Eric MANN, Grant MILLS
  • Patent number: 10848170
    Abstract: A method can include, amplifying an analog input signal to generate an amplified analog signal; modulating the amplified analog signal into a digital data stream; filtering the digital data stream with a first digital filter to generate a first filtered data stream, and selectively changing a gain of the amplifier in response to the first filtered data stream. While the digital data stream is filtered with the first digital filter, the digital data stream is filtered with a second digital filter to generate a second filtered data stream. An output digital value corresponding to the analog input signal in response to the second filtered data stream. Corresponding systems and devices are also disclosed.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: November 24, 2020
    Assignee: Cypress Semiconductor Corporation
    Inventors: Eashwar Thiagarajan, Erhan Hancioglu, Eric Mann, Harold Kutz, Amsby Richardson, Jr., Rajiv Singh
  • Publication number: 20180349425
    Abstract: Disclosed are system and methods for processing and storing data files, using a data edge file format. The data edge file separates information about what symbols are in a data file and information about the corresponding location of those symbols in the data file. The described technique for converting a source file comprising symbols into a data edge file includes: generating a locality file of symbol location from the source file to identify locations of the symbols in the source file, generating a symbol file to identify symbols in the source file, and then modifying the locality file of symbol location to associate each symbol from the symbol file with a location in the source file.
    Type: Application
    Filed: June 1, 2018
    Publication date: December 6, 2018
    Inventors: Thomas Hazel, David Noblet, Eric Mann, Grant Mills
  • Publication number: 20180351861
    Abstract: Devices and techniques for reorder resilient transport are described herein. A device may store data packets in sequential positions of a flow queue in an order in which the data packets were received. The device may retrieve a first data packet from a first sequential position and a second data packet from a second sequential position that is next in sequence to the first sequential position in the flow queue. The device may store the first data packet and the second data packet in a buffer and refrain from providing the first data packet and the second data packet to upper layer circuitry if the packet order information for the first data packet and the second data packet indicate that the first data packet and the second data packet were received out of order. Other embodiments are also described.
    Type: Application
    Filed: May 2, 2018
    Publication date: December 6, 2018
    Inventors: Anil Vasudevan, Parthasarathy Sarangam, Eric Mann, Daniel Cohn
  • Patent number: 9979640
    Abstract: Devices and techniques for reorder resilient transport are described herein. A device may store data packets in sequential positions of a flow queue in an order in which the data packets were received. The device may retrieve a first data packet from a first sequential position and a second data packet from a second sequential position that is next in sequence to the first sequential position in the flow queue. The device may store the first data packet and the second data packet in a buffer and refrain from providing the first data packet and the second data packet to upper layer circuitry if the packet order information for the first data packet and the second data packet indicate that the first data packet and the second data packet were received out of order. Other embodiments are also described.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: May 22, 2018
    Assignee: Intel Corporation
    Inventors: Anil Vasudevan, Parthasarathy Sarangam, Eric Mann, Daniel Cohn
  • Publication number: 20170068675
    Abstract: A method, a system, and a computer program product for adaptively managing information in a database management system are provided. The system generates a model associated with the database management system. The system receives information for performing a database. The system determines, based on the generated model and the database transaction, whether to adjust an attribute associated with the database management system.
    Type: Application
    Filed: July 13, 2016
    Publication date: March 9, 2017
    Inventors: Thomas HAZEL, Eric MANN, David NOBLET, Gerard BUTEAU
  • Patent number: 9503347
    Abstract: Examples are disclosed for determining or using server transaction latency information. In some examples, a network input/output device coupled to a server may be capable of time stamping information related to ingress request and egress response packets for a transaction. For these examples, elements of the server may be capable of determining transaction latency values based on the time stamped information. The determined transaction latency values may be used to monitor or manage operating characteristics of the server to include an amount of power provided to the server or an ability of the server to support one or more virtual servers. Other examples are described and claimed.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: November 22, 2016
    Assignee: INTEL CORPORATION
    Inventors: Manasi Deval, Jim Daubert, Eric Mann, Cong Li, Muralidhar Murali Rajappa, Anjaneya Reddy Chagam Reddy, David Wescott, Ramkumar Nagappan, Raed Kanjo
  • Publication number: 20160182369
    Abstract: Devices and techniques for reorder resilient transport are described herein. A device may store data packets in sequential positions of a flow queue in an order in which the data packets were received. The device may retrieve a first data packet from a first sequential position and a second data packet from a second sequential position that is next in sequence to the first sequential position in the flow queue. The device may store the first data packet and the second data packet in a buffer and refrain from providing the first data packet and the second data packet to upper layer circuitry if the packet order information for the first data packet and the second data packet indicate that the first data packet and the second data packet were received out of order. Other embodiments are also described.
    Type: Application
    Filed: December 23, 2014
    Publication date: June 23, 2016
    Inventors: Anil Vasudevan, Parthasarathy Sarangam, Eric Mann, Daniel Cohn
  • Publication number: 20150222516
    Abstract: Examples are disclosed for determining or using server transaction latency information. In some examples, a network input/output device coupled to a server may be capable of time stamping information related to ingress request and egress response packets for a transaction. For these examples, elements of the server may be capable of determining transaction latency values based on the time stamped information. The determined transaction latency values may be used to monitor or manage operating characteristics of the server to include an amount of power provided to the server or an ability of the server to support one or more virtual servers. Other examples are described and claimed.
    Type: Application
    Filed: December 18, 2012
    Publication date: August 6, 2015
    Inventors: Manasi Deval, Jim Daubert, Eric Mann, Cong Li, Muralidhar Murali Rajappa, Anjaneya Reddy Chagam Reddy, David Wescott, Ramkumar Nagappan, Raed Kanjo
  • Patent number: 8711096
    Abstract: A dual protocol input device for use with a host system is provided. In one embodiment, the input device comprises a chip with a number of semiconductor devices integrally formed thereon, including: an optical navigation sensor (ONS) to sense movement of the ONS relative to a surface; a wired protocol block to communicate data from the ONS to the host system by a wired communication protocol; a wireless protocol block to communicate data from the ONS to the host system by a wireless communication protocol; and a micro-controller coupled to the ONS, the wired protocol block and the wireless protocol block, to switch the input device between the wireless communication protocol and the wired communication protocol.
    Type: Grant
    Filed: March 27, 2009
    Date of Patent: April 29, 2014
    Assignee: Cypress Semiconductor Corporation
    Inventors: Ke-Cai Zeng, Jonathan Young, Pulkit Shah, Yansun Xu, Eric Mann, Shankar Subramani
  • Patent number: 7606623
    Abstract: Devices and methods were discovered that successfully provided patient autonomous control of both hyolaryngeal elevation, anterior hyoid motion and opening of the upper esophageal sphincter for swallowing by intramuscular stimulation of two muscles. The technology allows patient self stimulation of swallowing and can return oral feeding to dysphagia patients. Indwelling electrode stimulation of only two muscles generated as much as 80 % of normal synergistic movement leading to swallowing. The devices and methods also are useful for control of other upper respiratory muscle groups involved in speech and voice. Calibration techniques may be used in combination for greater freedom in setting and using electrodes over extended implantation time periods. These methods and devices can control complex movements of body solids such as bone and cartilage and tissues by electro stimulation of a minimum set of muscles simultaneously.
    Type: Grant
    Filed: September 26, 2003
    Date of Patent: October 20, 2009
    Assignee: The United States of America as represented by the Department of Health and Human Services
    Inventors: Christy L. Ludlow, Eric Mann, Theresa Burnett, Steven Bielamowicz
  • Publication number: 20070217409
    Abstract: An embodiment of the present invention is a technique to tag network transactions. A virtual queue stores packets received from and transmitted to a network interface card (NIC). A global session manager manages packet communication with a capability operating system (COS). A global virtual machine (VM) database stores global session identifiers (SIDs) of the packets and associated metadata. The global SIDs are used by the global session manager to track network sessions. The metadata describe characteristics of session connections. A VM tunnel connection encapsulates the packets passing to and from the COS.
    Type: Application
    Filed: March 20, 2006
    Publication date: September 20, 2007
    Inventor: Eric Mann