Abstract: A decimal floating-point instruction is executed in a round-for-reround mode. The decimal floating-point instruction is configured to perform a decimal floating-point operation on a decimal floating-point operand. The executing includes forming based on performing the decimal floating-point operation, an intermediate result having a high order portion and a low order portion. The high order portion has a least significant digit. A rounded-for-reround number is created from the intermediate result. The rounded-for-reround number includes the high order portion of the intermediate result and based on the least significant coefficient digit of the high order portion being a selected value and based on the low order portion having another selected value, the least significant digit of the rounded-for-reround number is incremented. The rounded-for-reround number is stored.

Abstract: An instruction is executed in round-for-reround mode wherein the permissible resultant value that is closest to and no greater in magnitude than the infinitely precise result is selected. If the selected value is not exact and the units digit of the selected value is either 0 or 5, then the digit is incremented by one and the selected value is delivered. In all other cases, the selected value is delivered.

Abstract: An instruction to perform converting and scaling operations is provided. Execution of the instruction includes converting an input value in one format to provide a converted result in another format. The converted result is scaled to provide a scaled result. A result obtained from the scaled result is placed in a selected location. Further, an instruction to perform scaling and converting operations is provided. Execution of the instruction includes scaling an input value in one format to provide a scaled result and converting the scaled result from the one format to provide a converted result in another format. A result obtained from the converted result is placed in a selected location.

Abstract: An instruction to perform an operation selected from a plurality of operations configured for the instruction is executed. The executing includes determining a value of a selected operand of the instruction. The determining the value is based on a control of the instruction and includes reading the selected operand of the instruction from a selected operand location to obtain the value of the selected operand, based on the control having a first value, and using a predetermined value as the value of the selected operand, based on the control having a second value. The value and another selected operand of the instruction are multiplied to obtain a product. An arithmetic operation is performed using the product and a chosen operand of the instruction to obtain an intermediate result. A result from the intermediate result is obtained and placed in a selected location.

Abstract: Vector pack and unpack instructions are described. An instruction to perform a conversion between one decimal format and another decimal format is executed, in which the one decimal format or the other decimal format is a zoned decimal format. The executing includes obtaining a value from at least one register specified using the instruction. At least a portion of the value is converted from the one decimal format to the other decimal format different from the one decimal format to provide a converted result. A result obtained from the converted result is written into a single register specified using the instruction.

Abstract: An instruction to perform an operation selected from a plurality of operations configured for the instruction is executed. The executing includes determining a value of a selected operand of the instruction. The determining the value is based on a control of the instruction and includes reading the selected operand of the instruction from a selected operand location to obtain the value of the selected operand, based on the control having a first value, and using a predetermined value as the value of the selected operand, based on the control having a second value. The value and another selected operand of the instruction are multiplied to obtain a product. An arithmetic operation is performed using the product and a chosen operand of the instruction to obtain an intermediate result. A result from the intermediate result is obtained and placed in a selected location.

Abstract: An instruction to perform converting and scaling operations is provided. Execution of the instruction includes converting an input value in one format to provide a converted result in another format. The converted result is scaled to provide a scaled result. A result obtained from the scaled result is placed in a selected location. Further, an instruction to perform scaling and converting operations is provided. Execution of the instruction includes scaling an input value in one format to provide a scaled result and converting the scaled result from the one format to provide a converted result in another format. A result obtained from the converted result is placed in a selected location.

Abstract: Vector pack and unpack instructions are described. An instruction to perform a conversion between one decimal format and another decimal format is executed, in which the one decimal format or the other decimal format is a zoned decimal format. The executing includes obtaining a value from at least one register specified using the instruction. At least a portion of the value is converted from the one decimal format to the other decimal format different from the one decimal format to provide a converted result. A result obtained from the converted result is written into a single register specified using the instruction.

Abstract: An instruction to perform scaling, converting and splitting operations is executed. The executing the instruction includes scaling an input value in one format to provide a scaled result. The scaled result is converted from the one format to provide a converted result in another format. The converted result is split into multiple parts, and one or more parts of the multiple parts are placed in a selected location.

Abstract: A method of instruction dispatch routing comprises receiving an instruction for dispatch to one of a plurality of issue queues; determining a priority status of the instruction; selecting a rotation order based on the priority status, wherein a first rotation order is associated with priority instructions and a second rotation order, different from the first rotation order, is associated with non-priority instructions; selecting an issue queue of the plurality of issue queues based on the selected rotation order; and dispatching the instruction to the selected issue queue.

Abstract: A method of instruction dispatch routing comprises receiving an instruction for dispatch to one of a plurality of issue queues; determining a priority status of the instruction; selecting a rotation order based on the priority status, wherein a first rotation order is associated with priority instructions and a second rotation order, different from the first rotation order, is associated with non-priority instructions; selecting an issue queue of the plurality of issue queues based on the selected rotation order; and dispatching the instruction to the selected issue queue.

Abstract: Aspects of the invention include receiving a first dictionary that includes key/value pairs for a first code listing. Key instances of the first dictionary include instruction addresses of the first code listing, and value instances of the first dictionary include hashes of data that uniquely identify instructions at the instruction addresses in the first code listing. A second dictionary that includes key/value pairs for a second code listing is received. Key instances of the second dictionary include hashes of data that uniquely identify instructions at instruction addresses in the second code listing, and value instances of the second dictionary include instruction addresses of the second code listing. A match between a value instance of the first dictionary and a key instance of the second dictionary is identified. Responsive to identifying the match, an instruction address is translated between the first code listing and the second code listing.

Abstract: An instruction is executed in round-for-reround mode wherein the permissible resultant value that is closest to and no greater in magnitude than the infinitely precise result is selected. If the selected value is not exact and the units digit of the selected value is either 0 or 5, then the digit is incremented by one and the selected value is delivered. In all other cases, the selected value is delivered.

Abstract: A two level branch history table (TLBHT) is substantially improved by providing a mechanism to prefetch entries from the very large second level branch history table (L2 BHT) into the active (very fast) first level branch history table (L1 BHT) before the processor uses them in the branch prediction process and at the same time prefetch cache misses into the instruction cache. The mechanism prefetches entries from the very large L2 BHT into the very fast L1 BHT before the processor uses them in the branch prediction process. A TLBHT is successful because it can prefetch branch entries into the L1 BHT sufficiently ahead of the time the entry is needed. This feature of the TLBHT is also used to prefetch instructions into the cache ahead of their use. In fact, the timeliness of the prefetches produced by the TLBHT can be used to remove most of the cycle time penalty incurred by cache misses.

Abstract: A floating point unit of an in-order-processor having a register array for storing a plurality of operands, a pipeline for executing floating point instructions with a plurality of stages, each stage having a stage register, data input registers (1A, 1B, 1C) for keeping operands to be processed. The data input registers form the first stage register of the pipeline. An input port loads operands from outside said floating point unit into one of said data input registers. A plurality of bypass-registers are provided, the input of which is connected to the input port, and the output of which is provided to the data input registers (1A, 1B, 1C), such that data propagating through the pipeline to be loaded into the register array can be immediately supplied to one or more particular data input registers (1A, 1B, 1C) from a respective bypass-register without a delay caused by additional pipeline stages to be propagated through.

Abstract: A two level branch history table (TLBHT) is substantially improved by providing a mechanism to prefetch entries from the very large second level branch history table (L2 BHT) into the active (very fast) first level branch history table (L1 BHT) before the processor uses them in the branch prediction process and at the same time prefetch cache misses into the instruction cache. The mechanism prefetches entries from the very large L2 BHT into the very fast L1 BHT before the processor uses them in the branch prediction process. A TLBHT is successful because it can prefetch branch entries into the L1 BHT sufficiently ahead of the time the entry is needed. This feature of the TLBHT is also used to prefetch instructions into the cache ahead of their use. In fact, the timeliness of the prefetches produced by the TLBHT can be used to remove most of the cycle time penalty incurred by cache misses.

Abstract: A computer processor floating point processor six cycle pipeline system where instruction text is fetched prior to the first cycle and decoded during the first cycle for the fetched particular instruction and the base (B) and index (X) register values are read for use in address generation. RXE Instructions are of the RX-type but extended by placing the extension of the operation code beyond the first four bytes of the instruction format and to assign the operation codes in such a way that the machine may determine the exact format from the first 8 bits of the operation code alone.

Abstract: A computer processor system having a floating point processor for instructions which are processed in a six cycle pipeline, in which prior to the first cycle of the pipeline an instruction text is fetched, and during the first cycle for the fetched particular instruction it is decoded and the base (B) and index (X) register values are read for use in address generation. Instructions of the RX-type are extended by placing the extension of the operation code beyond the first four bytes of the instruction format and to assign the operation codes in such a way that the machine may determine from the first 8 bits of the operation code alone, the exact format of the instruction. Instructions formats include the ESA/390 instructions SS, RR; RX; S; RRE; RI: and the new RXE instructions. where instructions of the RXE format have their R.sub.1, X.sub.2, B.sub.2, and D.sub.

Abstract: Preprocessing emulation methods utilizing search argument controls for a template routine address table in a target computing system. Target routines are stored in a target computing system for emulating incompatible instructions of an incompatible architecture which need not be recognized by the architecture of the target computing system. Preprocessing of template routines is preferrably executed on an Auxiliary Emulation Processor (AEP) which may access and patch (modify) some or all of the target instructions in any selected target routine and send them through a queue to a target processor for execution. Execution of the target routines on a target processor emulates the execution of incompatible instructions in an incompatible program in the incompatible architecture.

Abstract: An IEEE 754 standard floating point multiply instruction for binary extended precision format can be executed with a quad word format on an S/390 process. The multiplication calculation multiplies each partition by each other. In the multiplication calculation process dataflow process of either operand is a denormalized number, they are normalized at a stage which creates an expanded exponent range of one more bit, and the calculation continues to a parallel path multiplexor stage, but if neither operand is denormalized then the exponent of the number is expended and the calculation splits into four parallel paths, wherein two operand's sign bits are processed in a sign calculation block stage, the operands' two 16 bit binary exponents are processed by an exponent conversion block stage, and a partition multiplicand significand block stage receives a 113 bit multiplicand significand input for a fourth path.