Patents by Inventor Eric Masson

Eric Masson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11750226
    Abstract: Various embodiments include an error correction code (ECC) system that provides protection against various errors in addition to data bit errors. In general, ECC codes protect against data bit errors, where one or more data bits in a data word contain the wrong value. The ECC code is based on the original data bits, such that a data bit error results in a data word that is inconsistent with the ECC code generated for and stored with the data word. The present embodiments generate ECC codes based on address information and/or sequencing information in addition to the data bits in the data word. As a result, the present embodiments detect bit errors in this address information and/or sequencing information. Such errors include write address decoding errors, read address decoding errors, write enable errors, and stale data errors.
    Type: Grant
    Filed: June 9, 2021
    Date of Patent: September 5, 2023
    Assignee: NVIDIA CORPORATION
    Inventors: Eric Masson, Nagaraju Balasubramanya
  • Patent number: 11647227
    Abstract: Disclosed approaches may provide for non-blocking video processing pipelines that have the ability to efficiently share transform hardware resources. Transform hardware resources may be shared across processing parameters, such as pixel block dimensions, transform types, video stream bit depths, and/or multiple coding formats, as well as for inter-frame and intra-frame encoding. The video processing pipeline may be divided into phases, each phase having half-butterfly circuits to perform a respective portion of computations of a transform. The phases may be selectable and configurable to perform transforms for multiple different combinations of the processing parameters. In each configuration, the phases may be capable of performing a transform by a sequential pass through at least some of the phases resulting in high throughput. Approaches are also described related to improving the performance and efficiency of transpose operations of transforms.
    Type: Grant
    Filed: August 16, 2021
    Date of Patent: May 9, 2023
    Assignee: NVIDIA Corporation
    Inventors: Eric Masson, Ankur Saxena, Donald Bittel
  • Publication number: 20230062352
    Abstract: Disclosed approaches may provide for non-blocking video processing pipelines that have the ability to efficiently share transform hardware resources. Transform hardware resources may be shared across processing parameters, such as pixel block dimensions, transform types, video stream bit depths, and/or multiple coding formats, as well as for inter-frame and intra-frame encoding. The video processing pipeline may be divided into phases, each phase having half-butterfly circuits to perform a respective portion of computations of a transform. The phases may be selectable and configurable to perform transforms for multiple different combinations of the processing parameters. In each configuration, the phases may be capable of performing a transform by a sequential pass through at least some of the phases resulting in high throughput. Approaches are also described related to improving the performance and efficiency of transpose operations of transforms.
    Type: Application
    Filed: August 16, 2021
    Publication date: March 2, 2023
    Inventors: Eric Masson, Ankur Saxena, Donald Bittel
  • Publication number: 20220399905
    Abstract: Various embodiments include an error correction code (ECC) system that provides protection against various errors in addition to data bit errors. In general, ECC codes protect against data bit errors, where one or more data bits in a data word contain the wrong value. The ECC code is based on the original data bits, such that a data bit error results in a data word that is inconsistent with the ECC code generated for and stored with the data word. The present embodiments generate ECC codes based on address information and/or sequencing information in addition to the data bits in the data word. As a result, the present embodiments detect bit errors in this address information and/or sequencing information. Such errors include write address decoding errors, read address decoding errors, write enable errors, and stale data errors.
    Type: Application
    Filed: June 9, 2021
    Publication date: December 15, 2022
    Inventors: Eric MASSON, Nagaraju BALASUBRAMANYA
  • Patent number: 10753314
    Abstract: A nacelle includes a fixed structure supporting a fixed cowl and a movable cowl, the movable cowl being movable translationally between a closing position and an opening position. A blocker door is movably mounted rotationally on the nacelle between a closed position and an open position. The nacelle includes a drive mechanism of the blocker door and of the movable cowl between the closed/closing position and the open/opening position of the blocker door/movable cowl, respectively, and vice versa, the drive mechanism includes at least one actuator fixed, to the fixed structure of the nacelle and, to a fitting fixed to the movable cowl. The drive mechanism includes, for each actuator, a flexible member having a first end fixed to the fixed structure of the nacelle and a second end fixed to the fitting.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: August 25, 2020
    Assignees: Airbus Operations (S.A.S.), Airbus (S.A.S.)
    Inventors: Eric Haramburu, Patrick Oberle, Eric Masson
  • Publication number: 20180230939
    Abstract: A nacelle includes a fixed structure supporting a fixed cowl and a movable cowl, the movable cowl being movable translationally between a closing position and an opening position. A blocker door is movably mounted rotationally on the nacelle between a closed position and an open position. The nacelle includes a drive mechanism of the blocker door and of the movable cowl between the closed/closing position and the open/opening position of the blocker door/movable cowl, respectively, and vice versa, the drive mechanism includes at least one actuator fixed, to the fixed structure of the nacelle and, to a fitting fixed to the movable cowl. The drive mechanism includes, for each actuator, a flexible member having a first end fixed to the fixed structure of the nacelle and a second end fixed to the fitting.
    Type: Application
    Filed: February 6, 2018
    Publication date: August 16, 2018
    Inventors: Eric Haramburu, Patrick Oberle, Eric Masson
  • Patent number: 7909573
    Abstract: A casing cover for enclosing a casing in a jet engine is disclosed. The casing cover includes two coaxial shells arranged one inside the other and radial envelopes which connect the two coaxial shells. Radial arms of the casing extend inside the radial envelopes. The cover is fastened at its downstream end to a first element of the casing and axially abuts at its upstream end on a second element of the casing. In a free state, an axial dimension of the cover of less than the axial distance of the casing between the point where the first element of the casing is fastened to the downstream end of the cover and the point where the second element of the casing axially abuts the upstream end of the cover such that the cover is tensioned axially when it is mounted on and fastened to the casing.
    Type: Grant
    Filed: March 16, 2007
    Date of Patent: March 22, 2011
    Assignee: SNECMA
    Inventors: Laurent Bernard Cameriano, Sylvain Duval, Eric Masson, Herve Bernard Plisson
  • Publication number: 20070280034
    Abstract: A system and method for performing dynamic trimming. Specifically, the system comprises a clock for generating a reference clock signal. The reference clock signal comprises a first frequency that is a factor of a second frequency of a signal (e.g., data clock signal from DDR memory). A counter is coupled to the clock and generates a plurality of clock pulses based on pulses of the reference clock signal. The plurality of clock pulses is generated at a slower frequency from the first frequency for low power operation. A phase length detector is coupled to the counter and comprises a trimmer chain for detecting an average length of at least one of the generated plurality of clock pulses. A transformation module is coupled to the phase length detector for transforming the average length to a phase delay of the signal.
    Type: Application
    Filed: April 6, 2007
    Publication date: December 6, 2007
    Inventors: Eric Masson, Edward Ahn
  • Publication number: 20070217911
    Abstract: Casing cover (10) in a jet engine, comprising two coaxial shells (36, 38) arranged one inside the other and joined fixedly by radial envelopes (40) inside which extend radial arms (26) of the casing, the cover being fastened at its downstream end to an element of the casing and bearing axially at its upstream end on another element of the casing, and the cover having, in the free state, an axial dimension (D) of less than the axial distance (L) between the points where its downstream end is fastened to the casing and the points where its upstream end bears axially on the casing, and being tensioned axially when it is mounted on and fastened to the casing.
    Type: Application
    Filed: March 16, 2007
    Publication date: September 20, 2007
    Applicant: SNECMA
    Inventors: Laurent Bernard Cameriano, Sylvain Duval, Eric Masson, Herve Bernard Plisson
  • Publication number: 20070162743
    Abstract: An acoustical key generated from a finite random data source of a random acoustical signature, wherein a key generator generates the acoustical key. The key generator creates a bit field array of bit values from a data file and derives a plurality of intersection points of the array with the finite random data source to form the key with the bit values. In one embodiment, the data file is unaltered and the key can be used to authenticate the data file if used for data integrity. In another embodiment, at least one Tau offset may be used to establish a first bit value for said filling of the two dimensional array. In addition, at least one Phi offset may be used to establish a first key value for the key.
    Type: Application
    Filed: January 12, 2007
    Publication date: July 12, 2007
    Applicant: SAVANT PROTECTION, INC.
    Inventors: Kenneth Steinberg, Eric Masson
  • Publication number: 20050117828
    Abstract: The invention relates to a rotary shaft arrangement carrying equipment at one end and extending rearwards from the equipment, the shaft (1) being supported by a first bearing (2) behind the equipment, and by a second bearing (3) behind the first bearing (2), the first bearing (2) being carried by a casing (4) surrounding the shaft (1) and extending rearwards from the first bearing (2) to a stator structure (5) to which the casing (4) is fastened by screws (6) that extend parallel to the shaft (1) and that are fusible in traction, the arrangement being characterized by the fact that the second bearing (3) is disposed with radial clearance (J) in a bore (7) of an annular support (8) secured to the stator structure (5), and is fastened to said annular support (8) by screws (9) that are parallel to the shaft (1) and that are fusible in shear, whereby the second bearing (3) can bear against said support (8) in the event of said screws (9) rupturing.
    Type: Application
    Filed: October 24, 2002
    Publication date: June 2, 2005
    Inventors: Gael Bouchy, Bertrand Jean-Joseph Heurtel, Eric Masson, Bien-Aime Rakotodrainibe, Pierre Pandelakis, Daniel Martin, Patrick Morel, Henry Souyeaux