Patents by Inventor Eric Mattson

Eric Mattson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230197728
    Abstract: An integrated circuit includes a lower and upper device portions including bodies of semiconductor material extending horizontally between first source and drain regions in a spaced-apart vertical stack. A first gate structure is around a body in the lower device portion and includes a first gate electrode and a first gate dielectric. A second gate structure is around a body in the upper device portion and includes a second gate electrode and a second gate dielectric, where the first gate dielectric is compositionally distinct from the second gate dielectric. In some embodiments, a dipole species has a first concentration in the first gate dielectric and a different second concentration in the second gate dielectric. A method of fabrication is also disclosed.
    Type: Application
    Filed: December 17, 2021
    Publication date: June 22, 2023
    Applicant: Intel Corporation
    Inventors: Nicole K. Thomas, Eric Mattson, Sudarat Lee, Sarah Atanasov, Christopher J. Jezewski, Charles Mokhtarzadeh, Thoe Michaelos, I-Cheng Tung, Charles C. Kuo, Scott B. Clendenning, Matthew V. Metz
  • Publication number: 20230102219
    Abstract: Described herein are integrated circuit devices with metal-oxide semiconductor channels and carbon source and drain (S/D) contacts. S/D contacts conduct current to and from the semiconductor devices, e.g., to the source and drain regions of a transistor. Carbon S/D contacts may be particularly useful with semiconductor devices that use certain channel materials, such as indium gallium zinc oxide.
    Type: Application
    Filed: September 17, 2021
    Publication date: March 30, 2023
    Applicant: Intel Corporation
    Inventors: Arnab Sen Gupta, Matthew V. Metz, Hui Jae Yoo, Justin R. Weber, Van H. Le, Jason C. Retasket, Abhishek A. Sharma, Noriyuki Sato, Yu-Jin Chen, Eric Mattson, Edward O. Johnson, JR.
  • Publication number: 20220199620
    Abstract: Integrated circuitry comprising a ribbon or wire (RoW) transistor stack within which the transistors have different threshold voltages (Vt). In some examples, a gate electrode of the transistor stack may include only one workfunction metal. A metal oxide may be deposited around one or more channels of the transistor stack as a solid-state source of a metal oxide species that will diffuse toward the channel region(s). As diffused, the metal oxide may remain (e.g., as a silicate, or hafnate) in close proximity to the channel region, thereby altering the dipole properties of the gate insulator material. Different channels of a transistor stack may be exposed to differing amounts or types of the metal oxide species to provide a range of Vt within the stack. After diffusion, the metal oxide may be stripped as sacrificial, or retained.
    Type: Application
    Filed: December 18, 2020
    Publication date: June 23, 2022
    Applicant: Intel Corporation
    Inventors: Nicole Thomas, Eric Mattson, Sudarat Lee, Scott B. Clendenning, Tobias Brown-Heft, I-Cheng Tung, Thoe Michaelos, Gilbert Dewey, Charles Kuo, Matthew Metz, Marko Radosavljevic, Charles Mokhtarzadeh
  • Patent number: 9236633
    Abstract: A composition of graphene-based nanomaterials and a method of preparing the composition are provided. A carbon-based precursor is dissolved in water to form a precursor suspension. The precursor suspension is placed onto a substrate, thereby forming a precursor assembly. The precursor assembly is annealed, thereby forming the graphene-based nanomaterials. The graphene-based nanomaterials are crystallographically ordered at least in part and configured to form a plurality of diffraction rings when probed by an incident electron beam. In one aspect, the graphene-based nanomaterials are semiconducting. In one aspect, a method of engineering an energy bandgap of graphene monoxide generally includes providing at least one atomic layer of graphene monoxide having a first energy bandgap, and applying a substantially planar strain is applied to the graphene monoxide, thereby tuning the first energy band gap to a second energy bandgap.
    Type: Grant
    Filed: June 12, 2013
    Date of Patent: January 12, 2016
    Assignee: UWM Research Foundation, Inc.
    Inventors: Junhong Chen, Marija Gajdardziska-Josifovska, Carol Hirschmugl, Eric Mattson, Haihui Pu, Michael Weinert
  • Publication number: 20130344390
    Abstract: A composition of graphene-based nanomaterials and a method of preparing the composition are provided. A carbon-based precursor is dissolved in water to form a precursor suspension. The precursor suspension is placed onto a substrate, thereby forming a precursor assembly. The precursor assembly is annealed, thereby forming the graphene-based nanomaterials. The graphene-based nanomaterials are crystallographically ordered at least in part and configured to form a plurality of diffraction rings when probed by an incident electron beam. In one aspect, the graphene-based nanomaterials are semiconducting. In one aspect, a method of engineering an energy bandgap of graphene monoxide generally includes providing at least one atomic layer of graphene monoxide having a first energy bandgap, and applying a substantially planar strain is applied to the graphene monoxide, thereby tuning the first energy band gap to a second energy bandgap.
    Type: Application
    Filed: June 12, 2013
    Publication date: December 26, 2013
    Inventors: Junhong Chen, Marija Gajdardziska-Josifovska, Carol Hirschmugl, Eric Mattson, Haihui Pu, Michael Weinert