Abstract: A memory controller includes a generator circuit configured to generate a predetermined pattern of data, an address input, and a memory interface circuit. The memory interface circuit is configured to write the predetermined pattern of data to a memory at an address identified in the address input. The memory interface circuit is further configured to read a stored pattern of data from the memory at the address. The memory controller further includes an integrity checker circuit configured to compare the predetermined pattern of data and the stored pattern of data and identify an error of the memory based upon the comparison.

Abstract: An apparatus includes an interface for dynamic random access memory (DRAM); and an integrated circuit. The integrated circuit includes a memory pinout configured to connect to the memory and control logic. The control logic is configured multiplex address information, command information, and data to be written to or read from the DRAM memory on a subset of pins of the memory pinout to the DRAM memory. The control logic is further configured to route other signals on other pins of the memory pinout to the DRAM in parallel with the multiplexed address information, command information, and data information.

Abstract: An apparatus includes an interface for dynamic random access memory (DRAM); and an integrated circuit. The integrated circuit includes a memory pinout configured to connect to the memory and control logic. The control logic is configured multiplex address information, command information, and data to be written to or read from the DRAM memory on a subset of pins of the memory pinout to the DRAM memory. The control logic is further configured to route other signals on other pins of the memory pinout to the DRAM in parallel with the multiplexed address information, command information, and data information.

Abstract: A memory controller includes a generator circuit configured to generate a predetermined pattern of data, an address input, and a memory interface circuit. The memory interface circuit is configured to write the predetermined pattern of data to a memory at an address identified in the address input. The memory interface circuit is further configured to read a stored pattern of data from the memory at the address. The memory controller further includes an integrity checker circuit configured to compare the predetermined pattern of data and the stored pattern of data and identify an error of the memory based upon the comparison.

Abstract: A multi-matrix bus system is disclosed that provides proactive quality of service (QoS) by propagating, as soon as possible through an arbitration node in a network transfer request path, a highest priority value coming from an upstream arbitration node or master that has a current bus request pending at the arbitration node. The bus system ensures that any last downstream arbitration node knows at any time which is the highest priority request pending in the network transfer request path from the masters that are competing to share the bus layer switches and arbitration nodes in the network transfer request path.

Abstract: A multi-matrix bus system is disclosed that provides proactive quality of service (QoS) by propagating, as soon as possible through an arbitration node in a network transfer request path, a highest priority value coming from an upstream arbitration node or master that has a current bus request pending at the arbitration node. The bus system ensures that any last downstream arbitration node knows at any time which is the highest priority request pending in the network transfer request path from the masters that are competing to share the bus layer switches and arbitration nodes in the network transfer request path.

Abstract: A multi-matrix bus system is disclosed that provides proactive quality of service (QoS) by propagating, as soon as possible through an arbitration node in a network transfer request path, a highest priority value coming from an upstream arbitration node or master that has a current bus request pending at the arbitration node. The bus system ensures that any last downstream arbitration node knows at any time which is the highest priority request pending in the network transfer request path from the masters that are competing to share the bus layer switches and arbitration nodes in the network transfer request path.

Abstract: An apparatus for improving bandwidth for circuits having a plurality of memory controllers employing a first memory controller, a second memory controller, a first busy read output signal circuit, a first busy write output signal circuit, a second busy read output signal circuit, and a second busy write output signal circuit. The first busy read output signal indicates when the first memory controller releases the address bus for a next external access subsequent to a read access to the data bus by the first memory controller. The first busy write output signal indicates when the first memory controller releases the data bus for a next external access subsequent to a write access to the data bus by the first memory controller. The second busy read output signal indicates when the second memory controller releases the address bus for a next external access subsequent to a read access to the data bus by the second memory controller.

Abstract: A circuit for sampling data from a memory device comprises a circuit for providing a clock signal to the memory device, a data bus carrying data at twice the rate of the clock signal, a circuit for providing a control signal to indicate the period of time where data are valid, and a set of registers whose content is triggered by both edges of a signal resulting from the delay of the control signal. The set of registers is divided into several sub-parts, each sub-part loading the value of the data bus carrying data provided by the memory device at a period being an integer multiple of the clock signal where the sampling point is different for each sub-part.

Abstract: A circuit for providing a delayed clock signal to a synchronous memory controller controlling a synchronous memory device comprises logic delay circuitry for performing synchronous memory device read access, the logic delay circuitry generating delay interval information. A programmable delay line receives a clock signal and the delay interval information, the programmable delay line delaying the clock signal by the delay interval. A 2-input XOR gate receives both the clock signal and the output of the programmable delay line, an output of the XOR gate providing a delayed 2× clock signal.

Abstract: Various embodiments include method and apparatus for receiving a clock signal, determining a number of delay elements based on a relationship between the clock signal and a delayed feedback signal generated based on the clock signal, calculating an amount of time corresponding to the number of delay elements, and delaying a control signal by the amount of time to generate an additional clock signal, the control signal having a frequency higher than a frequency of the clock signal. Other embodiments are described.

Abstract: An apparatus for improving bandwidth for circuits having a plurality of memory controllers employing a first memory controller, a second memory controller, a first busy read output signal circuit, a first busy write output signal circuit, a second busy read output signal circuit, and a second busy write output signal circuit. The first busy read output signal indicates when the first memory controller releases the address bus for a next external access subsequent to a read access to the data bus by the first memory controller. The first busy write output signal indicates when the first memory controller releases the data bus for a next external access subsequent to a write access to the data bus by the first memory controller. The second busy read output signal indicates when the second memory controller releases the address bus for a next external access subsequent to a read access to the data bus by the second memory controller.

Abstract: Various apparatus and methods include a clock circuit to receive a first clock signal to generate a second clock signal having a frequency different from a frequency of the first clock signal. A clock capturing circuit receives the second clock signal for determining a number of delay elements corresponding to an amount of a period of the second clock signal. A delay calculation circuit calculates an amount of time corresponding to the number of delay elements. And a delay circuit delays an input control signal by the amount of time provided by the delay calculation circuit.

Abstract: A circuit for delaying an input control signal, comprises a clock circuit to generate a clock signal having a frequency different from an input clock signal to delay and including a clock signal input, a derivative clock signal output, an input to program a frequency ratio between its input clock frequency and its output clock frequency. A clock capturing circuit provides a determined number of delay elements required to provide a delay of an amount of the period of the signal provided by the clock circuit. A delay calculation circuit receives the determined number of delay elements and calculates a number of delay elements needed to delay the input control signal by an amount of time. A delay circuit includes a control signal input, a select input for receiving the number of delay elements provided by the delay calculation circuit.

Abstract: A circuit for providing a delayed clock signal to a synchronous memory controller controlling a synchronous memory device comprises logic delay circuitry for performing synchronous memory device read access, the logic delay circuitry generating delay interval information. A programmable delay line receives a clock signal and the delay interval information, the programmable delay line delaying the clock signal by the delay interval. A 2-input XOR gate receives both the clock signal and the output of the programmable delay line, an output of the XOR gate providing a delayed 2× clock signal.

Abstract: A method for delaying a control signal, includes receiving a clock signal, determining a number of delay elements required to generate a first delay equal to a target amount of the period of the clock signal, receiving a data signal having an edge generated at the same time as an edge of the control signal, determining a fraction number equal to the number of delay elements needed to generate a second delay for the data signal or the control signal to align their edges, divided by the number of cascaded delay elements necessary to provide a delay equal to the target amount of the period of the clock signal, multiplied by the number of delay elements to generate the first delay, and delaying the control signal by the number of cascaded delay elements to realize said first delay altered by the fraction number of delay elements.

Abstract: A circuit for providing a delayed clock signal to a synchronous memory controller controlling a synchronous memory device comprises logic delay circuitry for performing synchronous memory device read access, the logic delay circuitry generating delay interval information. A programmable delay line receives a clock signal and the delay interval information, the programmable delay line delaying the clock signal by the delay interval. A 2-input XOR gate receives both the clock signal and the output of the programmable delay line, an output of the XOR gate providing a delayed 2X clock signal.

Abstract: A circuit for providing a delayed clock signal to a synchronous memory controller controlling a synchronous memory device comprises logic delay circuitry for performing synchronous memory device read access, the logic delay circuitry generating delay interval information. A programmable delay line receives a clock signal and the delay interval information, the programmable delay line delaying the clock signal by the delay interval. A 2-input XOR gate receives both the clock signal and the output of the programmable delay line, an output of the XOR gate providing a delayed 2× clock signal.

Abstract: A method for delaying a control signal, includes receiving a clock signal, determining a number of delay elements required to generate a first delay equal to a target amount of the period of the clock signal, receiving a data signal having an edge generated at the same time as an edge of the control signal, determining a fraction number equal to the number of delay elements needed to generate a second delay for the data signal or the control signal to align their edges, divided by the number of cascaded delay elements necessary to provide a delay equal to the target amount of the period of the clock signal, multiplied by the number of delay elements to generate the first delay, and delaying the control signal by the number of cascaded delay elements to relaize said first delay altered by the fraction number of delay elements.

Abstract: A circuit for sampling data from a memory device comprises a circuit for providing a clock signal to the memory device, a data bus carrying data at twice the rate of the clock signal, a circuit for providing a control signal to indicate the period of time where data are valid, and a set of registers whose content is triggered by both edges of a signal resulting from the delay of the control signal. The set of registers is divided into several sub-parts, each sub-part loading the value of the data bus carrying data provided by the memory device at a period being an integer multiple of the clock signal where the sampling point is different for each sub-part.