Abstract: A network node includes a serial physical sublayer (PHY) chip, a parallel PHY chip, and a media access control (MAC) chip. The serial physical sublayer chip, includes a single bit transmit data input, a single bit receive data output, and serial PHY control signal input/output (I/O) lines. The parallel PHY chip includes a multi-bit transmit data input, a multi-bit receive data output, and parallel PHY control signal I/O lines. The MAC chip includes a multi-bit transmit data output, a multi-bit receive data input and parallel control signal I/O lines. The multi-bit transmit data output is connected to the multi-bit transmit data input. One bit of the multi-bit transmit data output is connected to the single bit transmit data input. The multi-bit receive data input is connected to the multi-bit receive data output. One bit of the multi-bit receive data input is connected to the single bit receive data output. The parallel control signal I/O lines are connected to the parallel PHY control signal I/O lines.

Abstract: A link control state machine controls a media access controller (MAC), a serial physical sublayer (serial PHY) and a media independent interface physical sublayer (MII PHY). In a first state of the link control state machine, an attempt is made to establish a link via the MII PHY. If successful, a second state is entered and the MAC performs data transfer using the MII PHY while the serial PHY is isolated from the MAC. In a third state, an attempt is made to establish a network link via a serial PHY. The MII PHY is isolated from the MAC and a test frame is sent using the serial PHY. The third state is entered from the first state when there is a link timeout on the MII PHY. In a fourth state, the MAC performs data transfer using the serial PHY. The fourth state is entered from the third state if the test frame was transmitted successfully.