Abstract: Technologies for backside structures on a quantum processor die are disclosed. In an illustrative embodiment, qubits are defined in a silicon layer of a semiconductor stack in a quantum processor die. Traces such as plunger gates, barrier gates, etc., can be positioned above and below the stack to interact with the qubits in various ways, such as by influencing a potential defining the qubits, shifting the resonance frequency of the qubits, causing oscillations in parameters such as physical position, electric field, magnetic field, etc. Static and/or dynamic voltages and/or currents may be applied to the traces, causing static and/or dynamic electric and/or magnetic fields to be applied to the qubits. The quantum processor die with such structure may be created using various techniques such as flip chip processing.

Abstract: Technologies for two-dimensional spin qubit arrays are disclosed. In an illustrative embodiment, a quantum processor die includes a two-dimensional array of spin qubits. Single-electron transistors (SETs) are arranged near an upper and lower boundary around the two-dimensional array of spin qubits. Each SET may be positioned to be able to read, e.g., qubits from two rows, allowing for the state of four rows of qubits to be read by the SETs above and below the array of qubits. The two-dimensional array of spin qubits may allow for a large number of physical and logical qubits in communication with each other, allowing for large scale quantum computation.