Patents by Inventor Eric Michael Verwillow

Eric Michael Verwillow has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • PROGRAMMING MODES FOR STORAGE DEVICES BASED ON DEVICE CHARACTERISTICS
    Publication number: 20260161299
    Abstract: A system operates solid-state storage memory. The system determines that a portion of the solid-state storage memory is of a type that has a failure mode of threshold voltage shift over time from successive reads at time intervals. The system alters or turns off a background process that performs such successive reads to check for memory reliability, for at least the portion of the solid-state storage memory. Or, the system uses the portion of solid-state storage memory for data bits, not parity bits.
    Type: Application
    Filed: January 22, 2026
    Publication date: June 11, 2026
    Inventors: HARI KANNAN, NENAD MILADINOVIC, ERIC MICHAEL VERWILLOW, DAVIS YEUNG
  • Managing voltage threshold shifts
    Patent number: 12547317
    Abstract: A system operates solid-state storage memory. The system determines that a portion of the solid-state storage memory is of a type that has a failure mode of threshold voltage shift over time from successive reads at time intervals. The system alters or turns off a background process that performs such successive reads to check for memory reliability, for at least the portion of the solid-state storage memory. Or, the system uses the portion of solid-state storage memory for data bits, not parity bits.
    Type: Grant
    Filed: April 16, 2021
    Date of Patent: February 10, 2026
    Assignee: PURE STORAGE, INC.
    Inventors: Hari Kannan, Nenad Miladinovic, Eric Michael Verwillow, Davis Yeung
  • MULTIPLE THRESHOLDS FOR MANAGING FLASH MEMORY
    Publication number: 20240420792
    Abstract: A method of tracking flash memory in a storage system is provided. The method includes initializing a bad blocks threshold value and marking one or more planes or logical unit numbers (LUNs) of flash memory as bad, responsive to determining that bad blocks in the one or more planes or LUNs meet the bad blocks threshold value. The method includes adjusting the bad blocks threshold value, responsive to exceeding a threshold number or rate of retiring planes or LUNs of flash memory, and repeating the marking and the adjusting, with the bad blocks threshold value capped at a maximum threshold value.
    Type: Application
    Filed: August 28, 2024
    Publication date: December 19, 2024
    Inventors: MATTHEW D. FLEMING, JOHN ROPER, HARI KANNAN, JOHN BOYLE, ERIC MICHAEL VERWILLOW, NENAD MILADINOVIC, ERIC MUELLER
  • Adaptive threshold for bad flash memory blocks
    Patent number: 12087382
    Abstract: A method of tracking flash memory in a storage system is provided. The method includes initializing a bad blocks threshold value and marking one or more planes or logical unit numbers (LUNs) of flash memory as bad, responsive to determining that bad blocks in the one or more planes or LUNs meet the bad blocks threshold value. The method includes adjusting the bad blocks threshold value, responsive to exceeding a threshold number or rate of retiring planes or LUNs of flash memory, and repeating the marking and the adjusting, with the bad blocks threshold value capped at a maximum threshold value.
    Type: Grant
    Filed: April 11, 2019
    Date of Patent: September 10, 2024
    Assignee: PURE STORAGE, INC.
    Inventors: Matthew D. Fleming, John Roper, Hari Kannan, John Boyle, Eric Michael Verwillow, Nenad Miladinovic, Eric Mueller
  • MANAGING VOLTAGE THRESHOLD SHIFTS
    Publication number: 20210232323
    Abstract: A system operates solid-state storage memory. The system determines that a portion of the solid-state storage memory is of a type that has a failure mode of threshold voltage shift over time from successive reads at time intervals. The system alters or turns off a background process that performs such successive reads to check for memory reliability, for at least the portion of the solid-state storage memory. Or, the system uses the portion of solid-state storage memory for data bits, not parity bits.
    Type: Application
    Filed: April 16, 2021
    Publication date: July 29, 2021
    Inventors: Hari Kannan, Nenad Miladinovic, Eric Michael Verwillow, Davis Yeung
  • ADAPTIVE THRESHOLD FOR BAD FLASH MEMORY BLOCKS
    Publication number: 20200327953
    Abstract: A method of tracking flash memory in a storage system is provided. The method includes initializing a bad blocks threshold value and marking one or more planes or logical unit numbers (LUNs) of flash memory as bad, responsive to determining that bad blocks in the one or more planes or LUNs meet the bad blocks threshold value. The method includes adjusting the bad blocks threshold value, responsive to exceeding a threshold number or rate of retiring planes or LUNs of flash memory, and repeating the marking and the adjusting, with the bad blocks threshold value capped at a maximum threshold value.
    Type: Application
    Filed: April 11, 2019
    Publication date: October 15, 2020
    Inventors: Matthew D. Fleming, John Roper, Hari Kannan, John Boyle, Eric Michael Verwillow, Nenad Miladinovic, Eric Mueller