Patents by Inventor Eric Miniere

Eric Miniere has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20260269761
    Abstract: The invention relates to the field of (digitally controlled) electric motors, (digital) control system, (electric) motor based system including those (digital) control system and methods pertaining thereto. The invention addresses the complexity of dynamically switching between two or more different modulation algorithms such as SVPWM (Space Vector Pulse Width Modulation), SPWM (Sinusoidal Pulse Width Modulation), THIPWM (Third Harmonic Pulse Width Modulation), DPWM (Discontinuous Pulse Width Modulation), OPP (Optimized Pulse Pattern).
    Type: Application
    Filed: May 16, 2023
    Publication date: September 10, 2026
    Inventors: Eric MINIERE, Farid TAHIRI, Khaled DOUZANE
  • Patent number: 8984347
    Abstract: A system, and in particular a system operating in real-time, may have its operation rely on a particular sequence of trigger signals, hardware or software, for proper operation. A trigger sequence checker provides a way to monitor in real-time predetermined sequences of triggers and is configured to generate an error signal upon detection of a faulty operation or sequence. Rules for sequences of triggers are stored in memory and are used by the trigger sequence checker to verify one or more sequences of triggers received as an input to the checker. A plurality of triggers may be handled by the checker. In one embodiment the checker is configurable to be set in a learning mode to capture triggers rules.
    Type: Grant
    Filed: October 17, 2012
    Date of Patent: March 17, 2015
    Assignee: Scaleo Chip
    Inventors: Bruno Salle, Eric Miniere
  • Publication number: 20140108856
    Abstract: A system, and in particular a system operating in real-time, may have its operation rely on a particular sequence of trigger signals, hardware or software, for proper operation. A trigger sequence checker provides a way to monitor in real-time predetermined sequences of triggers and is configured to generate an error signal upon detection of a faulty operation or sequence. Rules for sequences of triggers are stored in memory and are used by the trigger sequence checker to verify one or more sequences of triggers received as an input to the checker. A plurality of triggers may be handled by the checker. In one embodiment the checker is configurable to be set in a learning mode to capture triggers rules.
    Type: Application
    Filed: October 17, 2012
    Publication date: April 17, 2014
    Applicant: SCALEO CHIP
    Inventors: Bruno Salle, Eric Miniere