Abstract: A method and apparatus for performing a bus lock and a translation lookaside buffer invalidate transaction includes receiving, by a lock master, a lock request from a first processor in a system. The lock master sends a quiesce request to all processors in the system, and upon receipt of the quiesce request from the lock master, all processors cease issuing any new transactions and issue a quiesce granted transaction. Upon receipt of the quiesce granted transactions from all processors, the lock master issues a lock granted message that includes an identifier of the first processor. The first processor performs an atomic transaction sequence and sends a first lock release message to the lock master upon completion of the atomic transaction sequence. The lock master sends a second lock release message to all processors upon receiving the first lock release message from the first processor.

Abstract: A processor includes a set of processing modules, each of the processing modules including a cache and a coherency manager that keeps track of the memory addresses of data stored at the caches of other processing modules. In response to its local cache requesting access to a particular memory address or other triggering event, the coherency manager generates a coherency probe. In the event that the generated coherency probe is targeted to multiple processing modules, the coherency manager includes a set of multicast bits indicating the processing modules whose caches include copies of the data targeted by the multicast probe. A transport switch that connects the processing module to the fabric communicates the coherency probe only to subset of processing modules indicated by the multicast bits.

Abstract: A processor includes a set of processing modules, each of the processing modules including a cache and a coherency manager that keeps track of the memory addresses of data stored at the caches of other processing modules. In response to its local cache requesting access to a particular memory address or other triggering event, the coherency manager generates a coherency probe. In the event that the generated coherency probe is targeted to multiple processing modules, the coherency manager includes a set of multicast bits indicating the processing modules whose caches include copies of the data targeted by the multicast probe. A transport switch that connects the processing module to the fabric communicates the coherency probe only to subset of processing modules indicated by the multicast bits.

Abstract: A command replacement module at a coherency manager of a processor receives commands to be communicated over the communication fabric. For each received command of a specified type, the command replacement module compares a data payload of the command to a stored set of data patterns and, in response to a match, replaces the command with a replacement command, wherein the replacement command implies the contents of the data payload. The replacement command is communicated to the original commands destination via the communication fabric. In response to receiving the replacement command, the destination reconstructs the original command, deriving the data payload from the replacement command.

Abstract: A processor accumulating coherency probe responses, thereby reducing the impact of coherency messages on the bandwidth of the processor's communication fabric. A probe response accumulator is connected to a processing module of the processor, the processing module having multiple processor cores and associated caches. In response to a coherency probe, the processing module generates a different coherency probe response for each of the caches. The probe response accumulator combines the different coherency probe responses into a single coherency probe response and communicates the single coherency response over the communication fabric.

Abstract: A method and apparatus for performing a bus lock and a translation lookaside buffer invalidate transaction includes receiving, by a lock master, a lock request from a first processor in a system. The lock master sends a quiesce request to all processors in the system, and upon receipt of the quiesce request from the lock master, all processors cease issuing any new transactions and issue a quiesce granted transaction. Upon receipt of the quiesce granted transactions from all processors, the lock master issues a lock granted message that includes an identifier of the first processor. The first processor performs an atomic transaction sequence and sends a first lock release message to the lock master upon completion of the atomic transaction sequence. The lock master sends a second lock release message to all processors upon receiving the first lock release message from the first processor.

Abstract: An engine comprises a tank of compressed air and a piston. The tank of compressed air is connected to a conduit and the conduit is connected to a cylinder comprising a first valve and an inlet to a chamber. The chamber comprises the piston, which reciprocates. The chamber also has a second outlet connected to a second valve. The air traverses from the tank of compressed into the chamber by opening the first valve. Both the first valve and second valve are closed and the compressed air moves the piston in the chamber to produce work. The second valve opens and the air escapes from the chamber and the piston.

Abstract: An engine comprises a tank of compressed air and a piston. The tank of compressed air is connected to a conduit and the conduit is connected to a cylinder comprising a first valve and an inlet to a chamber. The chamber comprises the piston, which reciprocates. The chamber also has a second outlet connected to a second valve. The air traverses from the tank of compressed into the chamber by opening the first valve. Both the first valve and second valve are closed and the compressed air moves the piston in the chamber to produce work. The second valve opens and the air escapes from the chamber and the piston.

Abstract: A system includes a first device and a second device interconnected with a point-to-point link and operable to transmit data to each other via the point-to-point link. The first device is operable to provide data credits to the second device which facilitate transmission of the data to the first device via the point-to-point link in a plurality of virtual channels. First ones of the data credits are derived from a plurality of shared data credits each of which is operable to facilitate transmission of the data in any of the virtual channels. Second ones of the data credits include a plurality of dedicated data credits each of which is operable to facilitate transmission of the data in a corresponding one of the virtual channels.

Abstract: A computer system having a plurality of processing nodes interconnected by a first point-to-point architecture is described. Each processing node has a cache memory associated therewith. A probe filtering unit is operable to receive probes corresponding to memory lines from the processing nodes and to transmit the probes only to selected ones of the processing nodes with reference to probe filtering information. The probe filtering information is representative of states associated with selected ones of the cache memories.

Abstract: A computer system having a plurality of processing nodes interconnected by a first point-to-point architecture is described. Each processing node has a cache memory associated therewith. A probe filtering unit is operable to receive probes corresponding to memory lines from the processing nodes and to transmit the probes only to selected ones of the processing nodes with reference to probe filtering information. The probe filtering information is representative of states associated with selected ones of the cache memories.

Abstract: A system includes a first device and a second device interconnected with a point-to-point link and operable to transmit data to each other via the point-to-point link. The first device is operable to provide data credits to the second device which facilitate transmission of the data to the first device via the point-to-point link in a plurality of virtual channels. First ones of the data credits are derived from a plurality of shared data credits each of which is operable to facilitate transmission of the data in any of the virtual channels. Second ones of the data credits include a plurality of dedicated data credits each of which is operable to facilitate transmission of the data in a corresponding one of the virtual channels.