Patents by Inventor Eric N. Kaneshiro

Eric N. Kaneshiro has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6680497
    Abstract: A heterojunction bipolar transistor is doped in the sub-collector layer (20) with phosphorus (24). The presence of the phosphorus causes any interstitial gallium (22) to be bonded (26) to the phosphorus (24) and move to a lattice site. The result is that the interstitial gallium does not diffuse to the base layer and thus does not cause the beryllium to be displaced and diffused. Instead of doping with phosphorus, a layer including phosphorus can also be utilized.
    Type: Grant
    Filed: September 22, 2000
    Date of Patent: January 20, 2004
    Assignee: TRW Inc.
    Inventors: Patrick T. Chin, Augusto L. Gutierrez-Aitken, Eric N. Kaneshiro
  • Patent number: 6680494
    Abstract: Reduction in the base to collector capacitance of a heterojunction bipolar transistor, and, improved high frequency performance is achieved using existing materials and processes by undercutting the collector (5) under the base (7) along two parallel sides of the base mesa (7—FIG. 4), and providing a sloped collector edge (5—FIG. 6) along the remaining two parallel sides of the base. The foregoing is accomplished by selective etching and with the four sides of the mesa regions oriented as a non-rectangular parallelogram (7, 9—FIG. 4) in which one pair of sides is in parallel with one of the said [0 0 1] and [0 0 {overscore (1)}] planes of the crystalline structure and the other pair of sides in parallel with one of the [0 1 1] and [0 {overscore (1)} {overscore (1)}] planes of the crystalline structure.
    Type: Grant
    Filed: February 2, 2001
    Date of Patent: January 20, 2004
    Assignee: Northrop Grumman Corporation
    Inventors: Augusto L. Gutierrez-Aitken, Aaron K. Oki, Eric N. Kaneshiro, Dwight C. Streit
  • Publication number: 20010023947
    Abstract: Reduction in the base to collector capacitance of a heterojunction bipolar transistor, and, improved high frequency performance is achieved using existing materials and processes by undercutting the collector (5) under the base (7) along two parallel sides of the base mesa (7—FIG. 4), and providing a sloped collector edge (5—FIG. 6) along the remaining two parallel sides of the base. The foregoing is accomplished by selective etching and with the four sides of the mesa regions oriented as a non-rectangular parallelogram (7, 9—FIG. 4) in which one pair of sides is in parallel with one of the said [0 0 1] and [0 0 {overscore (1)}] planes of the crystalline structure and the other pair of sides in parallel with one of the [0 1 1] and [0 {overscore (1)} {overscore (1)}] planes of the crystalline structure.
    Type: Application
    Filed: February 2, 2001
    Publication date: September 27, 2001
    Inventors: Augusto L. Gutierrez-Aitken, Aaron K. Oki, Eric N. Kaneshiro, Dwight C. Streit