Abstract: A memory device can include a memory array including memory cells arranged in one or more pages. The memory array can be coupled to control logic to receive a first request to write first data to a page of the one or more pages and program the first data to the page of the one or more pages at a first time responsive to receiving the first request. The control logic is further to receive a second request to write second data to the page of the one or more pages, read the page of the one or more pages, and program the second data to the page of the one or more pages at a second time responsive to receiving the second request. The control logic can also receive an erase request to erase the one or more pages after the second time.

Abstract: A device includes non-volatile memory dies, a memory controller coupled to the non-volatile memory dies, a processing unit coupled to the memory controller and the non-volatile memory dies, and an external interface coupled, via a multiplexer controlled by the processing unit, to the non-volatile memory dies. The processing unit is configured to perform operations including: selecting, by the multiplexer, a first non-volatile memory die, causing the memory controller to read a data item from the first non-volatile memory die, and causing the data item to be transmitted via the external interface.

Abstract: A compute device comprising includes volatile memory (VM) dies stacked with a non-volatile memory (NVM) die and a logic die having control logic. A first plurality of through-silicon vias (TSVs) are formed through the one or more VM dies and the NVM die. In embodiments, the first plurality of TSVs are intercoupled through a plurality of microbumps. The control logic writes data to and reading data from the one or more VM dies through a first subset of the first plurality of TSVs. The control logic folds the data from the one or more VM dies to the NVM die through a second subset of the first plurality of TSVs that are fewer than the first subset and are dedicated to the folding of the data.

Abstract: A compute device includes a compute die, a on-chip cache with one or more volatile memory dies and one or more non-volatile memory dies, and a memory controller all disposed on the package substrate. The controller determines a first memory size requirement of one or more first operations executed by the compute die, determines that the first memory size requirement satisfies a threshold criterion, and responsive to determining that the first memory size requirement satisfies the threshold criterion, disables the one or more non-volatile memory dies in the on-chip cache.

Abstract: A compute device includes one or more volatile memory (VM) dies and a non-volatile memory (NVM) die, stacked with the VM dies. The NVM die includes a wide-bit input/output (I/O) interface. Through-silicon vias (TSVs) are formed through the VM dies and the NVM die and interconnected through microbumps. A logic die is stacked with the VM dies and the NVM die. The wide-bit I/O interface is configured to handle data transfers over the TSVs to and from the VM dies, through the logic die, at one of a data rate of the VM dies or at a reduced rate compared to the data rate of the VM dies.

Abstract: An example address translation method includes: receiving, by a controller of a memory device including one or more volatile memory dies and one or more non-volatile memory dies, a memory read request; responsive to determining that a logical memory address specified by the memory read request exceeds an upper limit of a user-addressable capacity of the one or more volatile memory dies, translating the logical memory address to a physical memory address identifying a transfer unit (TU) residing on a non-volatile memory die of one or more non-volatile memory dies; retrieving, from the non-volatile memory die, a data item stored by the TU identified by the physical memory address; storing the data item in a cache located on a volatile memory die of the one or more volatile memory dies; and transmitting the data item to the requestor.

Abstract: A compute device includes a compute die, a on-chip cache with one or more volatile memory dies and one or more non-volatile memory dies, and a memory controller all disposed on the package substrate. The controller separates read commands, received from the compute die, according to processing threads executed by the compute die and includes prediction engines and coupled performance monitors. A first prediction engine predicts, for a first processing thread, a first data access pattern associated with a first read command received from the first processing thread. A first performance monitor determines a first statistical value corresponding to a likelihood that the first prediction engine successfully predicted the first data access pattern. The first performance monitor, responsive to the first statistical value satisfying a threshold value, forwards a prefetch command consistent with the first data access pattern to a prefetch command manager for handling.

Abstract: A compute device includes a compute die disposed on a package substrate, and an on-chip cache disposed on the package substrate and coupled to the compute die. The on-chip cache includes volatile and non-volatile memory dies and a memory controller which is coupled between the compute die and the on-chip cache. The memory controller is configured to perform operations including receiving a request to write data to the on-chip cache, determining respective access bandwidths for the one or more volatile memory dies and the one or more non-volatile memory dies based on respective characteristics of the one or more volatile memory dies and the one or more non-volatile memory dies, and writing respective portions of the first data to the one or more volatile memory dies and the one or more non-volatile memory dies, wherein respective sizes of the respective portions are based on the respective access bandwidths.

Abstract: An example device includes a logic die, one or more volatile memory dies, one or more non-volatile memory dies, a plurality of through-silicon vias interconnecting the one or more volatile memory dies, the one or more non-volatile memory dies, and the logic die. The example device further includes a compute die, which in turn includes one or more processing units, and an interposer interconnecting the compute die and the logic die.

Abstract: Processing logic in a memory device receives a calibration scan command associated with the memory device. In response to the calibration scan command, execution of a set of read operations at a plurality of read voltage levels on the memory device is caused. In response to the calibration scan command, a set of bit counts is identified, where each bit count of the set of bit counts corresponds to a respective bin of a set of bins associated with the plurality of read voltage levels. Based on the bit count corresponding to each bin of the set of bins, a bin having a lowest bit count is identified.

Abstract: A system can include a processing device operatively coupled with the one or more memory devices, to perform operations that include writing data to the one or more memory devices and performing one or more scan operations on a management unit containing the data to determine a current value of a chosen data state metric. Each scan operation can be performed using a corresponding predetermined read-time parameter value. The operations can include determining whether the current value of the chosen data state metric satisfies a criterion, and can also include, responsive to determining that the current value of the chosen data state metric satisfies the criterion, selecting a remedial operation by determining whether redundancy metadata is included in a fault tolerant data stripe on the one or more memory devices. The operations can also include performing the remedial operation with respect to the management unit.

Abstract: A second read command to read second data from an array of memory cells is detected. An initial voltage to be applied to at least one wordline coupled to at least a subset of the array of memory cells is caused prior to releasing a first data associated with a first read command stored in a page buffer. The initial voltage to increase to a target value is caused. The page buffer to sense the second data from a bitline coupled to a page of the subset of the array of memory cells is caused. The sensed second data out of the bitline into the page buffer is read responsive to determining that the first data has been released from the page buffer.

Abstract: A memory device includes a first memory array, a second memory array, and a page cache circuit coupled to the first memory array and the second memory array. The page cache circuit includes at least one set of concurrent resources and at least one shared resource, wherein the at least one set of concurrent resources are asynchronously and concurrently accessible by the first memory array and the second memory array, and wherein the at least one shared resource is accessible in a time-multiplexed fashion by the first memory array and the second memory array.

Abstract: Control logic in a memory device selects two or more blocks of a plurality of blocks to concurrently scan during a scan operation. The control logic can further cause a first voltage to be applied to a dummy word line of each block of the two or more blocks to selectively couple a string of memory cells in each block of the two or more blocks to a different sense amplifier of a set of sense amplifiers coupled with the plurality of blocks. The control logic can cause a second voltage to be applied to a selected word line of each block of the two or more blocks to read a bit stored at a respective memory cell of the string of memory cells in each block out to the set of sense amplifier.

Abstract: A memory device can include a memory array including memory cells arranged in one or more pages. The memory array can be coupled to control logic to receive a first request to write first data to a page of the one or more pages and program the first data to the page of the one or more pages at a first time responsive to receiving the first request. The control logic is further to receive a second request to write second data to the page of the one or more pages, read the page of the one or more pages, and program the second data to the page of the one or more pages at a second time responsive to receiving the second request. The control logic can also receive an erase request to erase the one or more pages after the second time.

Abstract: A memory device includes a memory array and control logic, operatively coupled to the memory array, to perform operations including causing gate-induced drain leakage (GIDL) to be generated during a seeding operation of a program refresh operation, and causing, during the seeding operation, positive charge carriers generated by the GIDL to be transported to neutralize negative charge carriers generated by the program refresh operation.

Abstract: Systems and methods for two-stage memory cell programming. An example memory device comprises: a memory array; and a controller coupled to the memory array, the controller to perform operations comprising: receiving a request to perform a memory programming operation with respect to a target set of memory cells electrically coupled to a target wordline and a set of target bitlines; performing a first stage of the memory programming operation by causing a ramping up programming voltage to be applied to the target wordline while causing one or more pillars associated with the target memory cells to be boosted in a staggered manner; and performing a second stage of the memory programming operation by causing a programming voltage to be applied to the target wordline, while selectively applying bias voltage to the set of target bitlines.

Abstract: Memories might include an array of memory cells having a plurality of strings of series-connected memory cells each formed around a respective channel material structure, and a controller configured to determine a data state stored to a selected string of series-connected memory cells in response to charge stored to its respective channel material structure.

Abstract: Control logic in a memory device causes a pass voltage to be applied to a plurality of wordlines of a block of a memory array of the memory device, the block comprising a plurality of sub-blocks, and the pass voltage to boost a channel potential of each of the plurality of sub-blocks to a boost voltage. The control logic further selectively discharges the boost voltage from one or more of the plurality of sub-blocks according to a data pattern representing a sequence of bits to be programmed to respective memory cells of the plurality of sub-blocks. In addition, the control logic causes a single programming pulse to be applied to a selected wordline of the plurality of wordlines of the block to program the respective memory cells of the plurality of sub-blocks according to the data pattern.

Abstract: A memory device includes a memory array including wordlines and at least one string of cells. Each cell of the at least one string of cells is addressable by a respective wordline. The memory device further includes control logic, operatively coupled to the memory array, to perform operations including generating gate-induced drain leakage (GIDL) with respect to the at least one string of cells, and causing a grounding voltage to be applied to a set of wordlines to ground each cell of the at least one string of cells addressable by each wordline of the set of wordlines. The grounding voltage applied to the set of wordlines enables transport of positive charge carriers generated by the GIDL. In some embodiments, the positive charge carriers neutralize a buildup of negative charge carriers generated during a seeding phase of a program refresh operation.