Abstract: A memory array includes a block including wordlines, bitlines, and strings each connected to a respective bitline. The block is divided into a sub-blocks. Each sub-block includes a respective set of the strings, and each string of the set of strings is located at a sub-block position within its respective sub-block. Control logic performs operations including selecting each sub-block, causing a first voltage to be applied to a dummy wordline to activate a first set of dummy cells and deactivate a second set of dummy cells, and causing a second voltage to be applied to a selected wordline. Each sub-block includes a single string corresponding to an open string connected to a dummy cell of the first set of dummy cells. The second voltage causes data to be read out from each open string to a respective page buffer.

Abstract: A head-mounted device includes a display device that is configured to display content to a user, a support structure including a contact pad configured to engage a face of the user to support the display device with respect to the face of the user, a sensor that generates a sensor output signal, and a tension adjuster configured to move the contact pad relative to the support structure based on the sensor output signal to restrain motion of the display device with respect to the face of the user.

Abstract: Memory devices might include an array of memory cells, a plurality of access lines, and control logic. The array of memory cells includes a plurality of strings of series-connected memory cells. Each access line of the plurality of access lines is connected to a control gate of a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells. The control logic is configured to: open the array of memory cells for multiple read operations; read first page data from respective memory cells coupled to a selected access line of the plurality of access lines; read second page data from the respective memory cells coupled to the selected access line; and close the array of memory cells subsequent to reading the first page data and the second page data.

Abstract: Exemplary methods, apparatuses, and systems include a quick charge loss (QCL) mitigation manager for controlling writing data bits to a memory device. The QCL mitigation manager receives a first set of data bits for programming to memory. The QCL mitigation manager writes a first subset of data bits of the first set of data bits to a first memory block of the memory during a first pass of programming. The QCL mitigation manager writes a second subset of data bits of the first set of data bits to the first memory block during a second pass of programming in response to determining that the threshold delay is satisfied.

Abstract: A memory device includes a memory array and processing logic, operatively coupled with the memory array, to perform operations including causing a data transfer across an interface bus to be suspended by toggling a logical level of a control pin from a first level that activates the data transfer to a second level that suspends the data transfer, and causing the data transfer to resume by toggling the logical level of the control pin from the second level to the first level.

Abstract: Operations include monitoring a logical level of a first pin of the plurality of pins while a data burst is active, wherein the first pin is associated with at least one of a read enable signal or a data strobe signal, determining whether a period of time during which the logical level of the first pin is held at a first logical level satisfies a threshold condition, in response to determining that the period of time satisfies the threshold condition, continuing to monitor the logical level of the first pin, determining whether the logical level of the first pin changed from the first logical level to a second logical level, and in response to determining that the logical level of the first pin changed from the first logical to the second logical level, causing warmup cycles to be performed.

Abstract: A system can include a processing device operatively coupled with the one or more memory devices, to perform operations that include writing data to the one or more memory devices and performing one or more scan operations on a management unit containing the data to determine a current value of a chosen data state metric. Each scan operation can be performed using a corresponding predetermined read-time parameter value. The operations can include determining whether the current value of the chosen data state metric satisfies a criterion, and can also include, responsive to determining that the current value of the chosen data state metric satisfies the criterion, selecting a remedial operation by determining whether redundancy metadata is included in a fault tolerant data stripe on the one or more memory devices. The operations can also include performing the remedial operation with respect to the management unit.

Abstract: Processing logic in a memory device receives a calibration scan command associated with the memory device. In response to the calibration scan command, execution of a set of read operations at a plurality of read voltage levels on the memory device is caused. In response to the calibration scan command, a set of bit counts is identified, where each bit count of the set of bit counts corresponds to a respective bin of a set of bins associated with the plurality of read voltage levels. Based on the bit count corresponding to each bin of the set of bins, a bin having a lowest bit count is identified.

Abstract: Control logic in a memory device identifies a set of memory cells in a block of a memory array, wherein the set of memory cells comprises two or more memory cells programmed during a program phase of a program operation and associated with a selected wordline of the memory array. The control logic further causes a program verify voltage to be applied to the selected wordline during a program verify phase of the program operation and performs concurrent sensing operations on the set of memory cells to determine whether each memory cell in the set of memory cells was programmed to at least the program verify voltage during the program phase of the program operation.

Abstract: Memory devices might include an array of memory cells, a plurality of access lines, and control logic. The array of memory cells includes a plurality of strings of series-connected memory cells. Each access line of the plurality of access lines is connected to a control gate of a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells. The control logic is configured to: open the array of memory cells for multiple read operations; read first page data from respective memory cells coupled to a selected access line of the plurality of access lines; read second page data from the respective memory cells coupled to the selected access line; and close the array of memory cells subsequent to reading the first page data and the second page data.

Abstract: A second read command to read second data from an array of memory cells is detected. An initial voltage to be applied to at least one wordline coupled to at least a subset of the array of memory cells is caused prior to releasing a first data associated with a first read command stored in a page buffer. The initial voltage to increase to a target value is caused. The page buffer to sense the second data from a bitline coupled to a page of the subset of the array of memory cells is caused. The sensed second data out of the bitline into the page buffer is read responsive to determining that the first data has been released from the page buffer.

Abstract: Exemplary methods, apparatuses, and systems include a quick charge loss (QCL) mitigation manager for controlling writing data bits to a memory device. The QCL mitigation manager receives a first set of data bits for programming to memory. The QCL mitigation manager writes a first subset of data bits of the first set of data bits to a first memory block of the memory during a first pass of programming. The QCL mitigation manager writes a second subset of data bits of the first set of data bits to the first memory block during a second pass of programming in response to determining that the threshold delay is satisfied.

Abstract: A memory device includes a memory array and processing logic, operatively coupled with the memory array, to perform operations including causing a data burst to be initiated by toggling a logical level of a control pin from a first level corresponding to a data burst inactive mode to a second level corresponding to a data burst active mode, wherein the data burst corresponds to a data transfer across an interface bus, causing the data burst to be suspended by toggling the logical level of the control pin from the second level to a third level corresponding to a data burst suspend mode, and causing the data burst to be resumed by toggling the logical level of the control pin from the third level to the second level.

Abstract: A system can include a processing device operatively coupled with the one or more memory devices, to perform operations that include writing data to the one or more memory devices and performing one or more scan operations on a management unit containing the data to determine a current value of a chosen data state metric. Each scan operation can be performed using a corresponding predetermined read-time parameter value. The operations can include determining whether the current value of the chosen data state metric satisfies a criterion, and can also include, responsive to determining that the current value of the chosen data state metric satisfies the criterion, selecting a remedial operation by determining whether redundancy metadata is included in a fault tolerant data stripe on the one or more memory devices. The operations can also include performing the remedial operation with respect to the management unit.

Abstract: A request to execute a programming operation to program multiple sub-blocks including a first sub-block and a second sub-block of a memory device is identified. A first drive operation is executed to load first data into a first select gate drain (SGD) associated with the first sub-block. Following completion of the first drive operation, a second drive operation is executed to load second data into a second SGD associated with the second sub-block. Following completion of the second drive operation, a third drive operation is executed to re-load the first data into the first SGD.

Abstract: An apparatus is provided, comprising a substrate with a frontside and a backside opposite the frontside; control circuitry disposed over the frontside of the substrate; a memory array disposed over and electrically coupled to the control circuitry; a through-silicon via (TSV) disposed under the memory array, the TSV extending through the substrate from the control circuitry to the backside of the substrate; and a bond pad disposed on the backside of the substrate and electrically coupled to the control circuitry via the TSV.

Abstract: A memory device includes a first memory array, a second memory array, and a page cache circuit coupled to the first memory array and the second memory array. The page cache circuit includes at least one set of concurrent resources and at least one shared resource, wherein the at least one set of concurrent resources are asynchronously and concurrently accessible by the first memory array and the second memory array, and wherein the at least one shared resource is accessible in a time-multiplexed fashion by the first memory array and the second memory array.

Abstract: A request to execute a programming operation to program multiple sub-blocks including a first sub-block and a second sub-block of a memory device is identified. A first drive operation is executed to load first data into a first select gate drain (SGD) associated with the first sub-block. One or more program bias disturb mitigation operations are executed in association with a second drive operation to load second data into a second SGD associated with the second sub-block.

Abstract: Control logic in a memory device identifies a set of memory cells in a block of a memory array, wherein the set of memory cells comprises two or more memory cells programmed during a program phase of a program operation and associated with a selected wordline of the memory array. The control logic further causes a program verify voltage to be applied to the selected wordline during a program verify phase of the program operation and performs concurrent sensing operations on the set of memory cells to determine whether each memory cell in the set of memory cells was programmed to at least the program verify voltage during the program phase of the program operation.

Abstract: Processing logic in a memory device receives a command to execute a set of read operations having read voltage levels corresponding to a programming distribution associated with the memory device. A set of memory bit counts is determined, where each memory bit count corresponds to a respective bin of a set of bins associated with the multiple read voltage levels of the set of read operations. A valley center bin having a minimum memory bit count of the set of memory bit counts is determined. The processing logic determines that the minimum memory bit count of the valley center bin satisfies a condition and an adjusted read voltage level associated with the valley center bin is identified in response to the condition being satisfied.