Patents by Inventor Eric N. Lee

Eric N. Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12266407
    Abstract: A method includes causing a read operation to be initiated with respect to a set of target cells. For each target cell, a respective group of adjacent cells is adjacent to the target cell. The method further includes obtaining, for each group of adjacent cells, respective cell state information, assigning, based on the cell state information, each target cell of the set of target cells to a respective state information bin, and determining a set of calibrated read level offsets. Each state information bin is associated with a respective group of target cells of the set of target cells, and each calibrated read level offset of the set of calibrated read level offsets is associated with a respective state information bin of the set of state information bins.
    Type: Grant
    Filed: April 18, 2023
    Date of Patent: April 1, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Tomoharu Tanaka, James Fitzpatrick, Huai-Yuan Tseng, Kishore Kumar Muchherla, Eric N. Lee, David Scott Ebsen, Dung Viet Nguyen, Akira Goda
  • Patent number: 12249364
    Abstract: Methods, apparatuses and systems related to maintaining stored data are described. The apparatus may be configured to refresh the stored data according to schedule that includes different delays between successive refresh operations.
    Type: Grant
    Filed: August 17, 2022
    Date of Patent: March 11, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Huai-Yuan Tseng, Akira Goda, Kishore Kumar Muchherla, James Fitzpatrick, Tomoharu Tanaka, Eric N. Lee, Dung V. Nguyen, David Ebsen
  • Patent number: 12248411
    Abstract: Operations include establishing a queue storing a list of data burst commands to be communicated via a multiplexed interface coupled to the set of memory dies, communicating, during a first time period, a first data burst command in the queue to a first memory die of the set of memory dies via the multiplexed interface, and communicating, during a second time period, a second data burst command in the queue to a second memory die of the set of memory dies via the multiplexed interface, where a first latency associated with the first data burst command occurs during the second time period.
    Type: Grant
    Filed: May 9, 2023
    Date of Patent: March 11, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Eric N. Lee, Luigi Pilolli, Ali Feiz Zarrin Ghalam, Xiangyu Tang, Daniel Jerre Hubbard
  • Publication number: 20250077416
    Abstract: A memory device can include a memory array including memory cells arranged in one or more pages. The memory array can be coupled to control logic to receive a first request to write first data to a page of the one or more pages and program the first data to the page of the one or more pages at a first time responsive to receiving the first request. The control logic is further to receive a second request to write second data to the page of the one or more pages, read the page of the one or more pages, and program the second data to the page of the one or more pages at a second time responsive to receiving the second request. The control logic can also receive an erase request to erase the one or more pages after the second time.
    Type: Application
    Filed: July 23, 2024
    Publication date: March 6, 2025
    Inventors: Huai-Yuan Tseng, Xiangyu Tang, Eric N. Lee, Haibo Li, Kishore Kumar Muchherla, Akira Goda
  • Publication number: 20250077455
    Abstract: Operations include determining, based on a period of time during which a logical level of the signal line is maintained at a first logical level, that a data transfer to the memory array is being suspended, determining, while the data transfer is suspended, whether the logical level of the signal line has changed from the first logical level to a second logical level, and in response to determining that the logical level of the signal line has changed from the first logical level to the second logical level, causing warm-up cycles to be performed.
    Type: Application
    Filed: November 19, 2024
    Publication date: March 6, 2025
    Inventors: Eric N. Lee, Leonid Minz, Yoav Weinberg, Ali Feiz Zarrin Ghalam, Luigi Pilolli
  • Patent number: 12237018
    Abstract: A method includes receiving signaling indicative of performance of a sanitization operation to a processing device coupled to a memory device and applying a sanitization voltage to a plurality of memory blocks of the memory device. The sanitization voltage can be greater than an erase voltage of the plurality of memory blocks.
    Type: Grant
    Filed: November 3, 2023
    Date of Patent: February 25, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Eric N. Lee, Robert W. Strong, William Akin, Jeremy Binfet
  • Patent number: 12217799
    Abstract: A memory array includes a block including wordlines, bitlines, and strings each connected to a respective bitline. The block is divided into a sub-blocks. Each sub-block includes a respective set of the strings, and each string of the set of strings is located at a sub-block position within its respective sub-block. Control logic performs operations including selecting each sub-block, causing a first voltage to be applied to a dummy wordline to activate a first set of dummy cells and deactivate a second set of dummy cells, and causing a second voltage to be applied to a selected wordline. Each sub-block includes a single string corresponding to an open string connected to a dummy cell of the first set of dummy cells. The second voltage causes data to be read out from each open string to a respective page buffer.
    Type: Grant
    Filed: March 10, 2023
    Date of Patent: February 4, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Paing Z. Htet, Akira Goda, Eric N. Lee, Jeffrey S. McNeil, Junwyn A. Lacsao, Kishore Kumar Muchherla, Sead Zildzic, Violante Moschiano
  • Publication number: 20250035942
    Abstract: A head-mounted device includes a display device that is configured to display content to a user, a support structure including a contact pad configured to engage a face of the user to support the display device with respect to the face of the user, a sensor that generates a sensor output signal, and a tension adjuster configured to move the contact pad relative to the support structure based on the sensor output signal to restrain motion of the display device with respect to the face of the user.
    Type: Application
    Filed: October 14, 2024
    Publication date: January 30, 2025
    Inventors: Grant H. Mulliken, David A. Kalinowski, Brandon R. Neale, David A. Schmuck, Eric N. Vergo, Jae Hwang Lee
  • Publication number: 20250029641
    Abstract: Memory devices might include an array of memory cells, a plurality of access lines, and control logic. The array of memory cells includes a plurality of strings of series-connected memory cells. Each access line of the plurality of access lines is connected to a control gate of a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells. The control logic is configured to: open the array of memory cells for multiple read operations; read first page data from respective memory cells coupled to a selected access line of the plurality of access lines; read second page data from the respective memory cells coupled to the selected access line; and close the array of memory cells subsequent to reading the first page data and the second page data.
    Type: Application
    Filed: October 9, 2024
    Publication date: January 23, 2025
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Eric N. Lee, Kishore Kumar Muchherla, Jeffrey S. MCNeil, Jung-Sheng Hoei
  • Publication number: 20250013382
    Abstract: Exemplary methods, apparatuses, and systems include a quick charge loss (QCL) mitigation manager for controlling writing data bits to a memory device. The QCL mitigation manager receives a first set of data bits for programming to memory. The QCL mitigation manager writes a first subset of data bits of the first set of data bits to a first memory block of the memory during a first pass of programming. The QCL mitigation manager writes a second subset of data bits of the first set of data bits to the first memory block during a second pass of programming in response to determining that the threshold delay is satisfied.
    Type: Application
    Filed: September 24, 2024
    Publication date: January 9, 2025
    Inventors: Kishore Kumar Muchherla, Dung V. Nguyen, Dave Scott Ebsen, Tomoharu Tanaka, James Fitzpatrick, Huai-Yuan Tseng, Akira Goda, Eric N. Lee
  • Publication number: 20250004962
    Abstract: A memory device includes a memory array and processing logic, operatively coupled with the memory array, to perform operations including causing a data transfer across an interface bus to be suspended by toggling a logical level of a control pin from a first level that activates the data transfer to a second level that suspends the data transfer, and causing the data transfer to resume by toggling the logical level of the control pin from the second level to the first level.
    Type: Application
    Filed: September 10, 2024
    Publication date: January 2, 2025
    Inventors: Eric N. Lee, Leonid Minz, Yoav Weinberg, Ali Feiz Zarrin Ghalam, Luigi Pilolli
  • Patent number: 12182046
    Abstract: Operations include monitoring a logical level of a first pin of the plurality of pins while a data burst is active, wherein the first pin is associated with at least one of a read enable signal or a data strobe signal, determining whether a period of time during which the logical level of the first pin is held at a first logical level satisfies a threshold condition, in response to determining that the period of time satisfies the threshold condition, continuing to monitor the logical level of the first pin, determining whether the logical level of the first pin changed from the first logical level to a second logical level, and in response to determining that the logical level of the first pin changed from the first logical to the second logical level, causing warmup cycles to be performed.
    Type: Grant
    Filed: March 9, 2023
    Date of Patent: December 31, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Eric N. Lee, Leonid Minz, Yoav Weinberg, Ali Feiz Zarrin Ghalam, Luigi Pilolli
  • Publication number: 20240402922
    Abstract: A system can include a processing device operatively coupled with the one or more memory devices, to perform operations that include writing data to the one or more memory devices and performing one or more scan operations on a management unit containing the data to determine a current value of a chosen data state metric. Each scan operation can be performed using a corresponding predetermined read-time parameter value. The operations can include determining whether the current value of the chosen data state metric satisfies a criterion, and can also include, responsive to determining that the current value of the chosen data state metric satisfies the criterion, selecting a remedial operation by determining whether redundancy metadata is included in a fault tolerant data stripe on the one or more memory devices. The operations can also include performing the remedial operation with respect to the management unit.
    Type: Application
    Filed: August 15, 2024
    Publication date: December 5, 2024
    Inventors: Kishore Kumar Muchherla, Robert Loren O. Ursua, Sead Zildzic, Eric N. Lee, Jonathan S. Parry, Lakshmi Kalpana K. Vakati, Jeffrey S. McNeil
  • Publication number: 20240395338
    Abstract: Processing logic in a memory device receives a calibration scan command associated with the memory device. In response to the calibration scan command, execution of a set of read operations at a plurality of read voltage levels on the memory device is caused. In response to the calibration scan command, a set of bit counts is identified, where each bit count of the set of bit counts corresponds to a respective bin of a set of bins associated with the plurality of read voltage levels. Based on the bit count corresponding to each bin of the set of bins, a bin having a lowest bit count is identified.
    Type: Application
    Filed: July 31, 2024
    Publication date: November 28, 2024
    Inventors: Eric N. Lee, Violante Moschiano, Jeffrey S. McNeil, James Fitzpatrick, Sivagnanam Parthasarathy, Kishore Kumar Muchherla, Patrick R. Khayat
  • Publication number: 20240379178
    Abstract: Control logic in a memory device identifies a set of memory cells in a block of a memory array, wherein the set of memory cells comprises two or more memory cells programmed during a program phase of a program operation and associated with a selected wordline of the memory array. The control logic further causes a program verify voltage to be applied to the selected wordline during a program verify phase of the program operation and performs concurrent sensing operations on the set of memory cells to determine whether each memory cell in the set of memory cells was programmed to at least the program verify voltage during the program phase of the program operation.
    Type: Application
    Filed: July 22, 2024
    Publication date: November 14, 2024
    Inventors: Eric N. Lee, Tomoko Ogura Iwasaki
  • Patent number: 12142343
    Abstract: Memory devices might include an array of memory cells, a plurality of access lines, and control logic. The array of memory cells includes a plurality of strings of series-connected memory cells. Each access line of the plurality of access lines is connected to a control gate of a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells. The control logic is configured to: open the array of memory cells for multiple read operations; read first page data from respective memory cells coupled to a selected access line of the plurality of access lines; read second page data from the respective memory cells coupled to the selected access line; and close the array of memory cells subsequent to reading the first page data and the second page data.
    Type: Grant
    Filed: August 11, 2023
    Date of Patent: November 12, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Eric N. Lee, Kishore Kumar Muchherla, Jeffrey S. McNeil, Jung-Sheng Hoei
  • Publication number: 20240361929
    Abstract: A second read command to read second data from an array of memory cells is detected. An initial voltage to be applied to at least one wordline coupled to at least a subset of the array of memory cells is caused prior to releasing a first data associated with a first read command stored in a page buffer. The initial voltage to increase to a target value is caused. The page buffer to sense the second data from a bitline coupled to a page of the subset of the array of memory cells is caused. The sensed second data out of the bitline into the page buffer is read responsive to determining that the first data has been released from the page buffer.
    Type: Application
    Filed: July 10, 2024
    Publication date: October 31, 2024
    Inventors: Sundararajan Sankaranarayanan, Eric N. Lee
  • Patent number: 12131060
    Abstract: Exemplary methods, apparatuses, and systems include a quick charge loss (QCL) mitigation manager for controlling writing data bits to a memory device. The QCL mitigation manager receives a first set of data bits for programming to memory. The QCL mitigation manager writes a first subset of data bits of the first set of data bits to a first memory block of the memory during a first pass of programming. The QCL mitigation manager writes a second subset of data bits of the first set of data bits to the first memory block during a second pass of programming in response to determining that the threshold delay is satisfied.
    Type: Grant
    Filed: July 25, 2022
    Date of Patent: October 29, 2024
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Kishore Kumar Muchherla, Dung V. Nguyen, Dave Scott Ebsen, Tomoharu Tanaka, James Fitzpatrick, Huai-Yuan Tseng, Akira Goda, Eric N. Lee
  • Patent number: 12111781
    Abstract: A memory device includes a memory array and processing logic, operatively coupled with the memory array, to perform operations including causing a data burst to be initiated by toggling a logical level of a control pin from a first level corresponding to a data burst inactive mode to a second level corresponding to a data burst active mode, wherein the data burst corresponds to a data transfer across an interface bus, causing the data burst to be suspended by toggling the logical level of the control pin from the second level to a third level corresponding to a data burst suspend mode, and causing the data burst to be resumed by toggling the logical level of the control pin from the third level to the second level.
    Type: Grant
    Filed: March 9, 2023
    Date of Patent: October 8, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Eric N. Lee, Leonid Minz, Yoav Weinberg, Ali Feiz Zarrin Ghalam, Luigi Pilolli
  • Patent number: 12105967
    Abstract: A system can include a processing device operatively coupled with the one or more memory devices, to perform operations that include writing data to the one or more memory devices and performing one or more scan operations on a management unit containing the data to determine a current value of a chosen data state metric. Each scan operation can be performed using a corresponding predetermined read-time parameter value. The operations can include determining whether the current value of the chosen data state metric satisfies a criterion, and can also include, responsive to determining that the current value of the chosen data state metric satisfies the criterion, selecting a remedial operation by determining whether redundancy metadata is included in a fault tolerant data stripe on the one or more memory devices. The operations can also include performing the remedial operation with respect to the management unit.
    Type: Grant
    Filed: August 24, 2022
    Date of Patent: October 1, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Kishore Kumar Muchherla, Robert Loren O. Ursua, Sead Zildzic, Eric N. Lee, Jonathan S. Parry, Lakshmi Kalpana K. Vakati, Jeffrey S. McNeil