Patents by Inventor Eric N. Lee
Eric N. Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240402922Abstract: A system can include a processing device operatively coupled with the one or more memory devices, to perform operations that include writing data to the one or more memory devices and performing one or more scan operations on a management unit containing the data to determine a current value of a chosen data state metric. Each scan operation can be performed using a corresponding predetermined read-time parameter value. The operations can include determining whether the current value of the chosen data state metric satisfies a criterion, and can also include, responsive to determining that the current value of the chosen data state metric satisfies the criterion, selecting a remedial operation by determining whether redundancy metadata is included in a fault tolerant data stripe on the one or more memory devices. The operations can also include performing the remedial operation with respect to the management unit.Type: ApplicationFiled: August 15, 2024Publication date: December 5, 2024Inventors: Kishore Kumar Muchherla, Robert Loren O. Ursua, Sead Zildzic, Eric N. Lee, Jonathan S. Parry, Lakshmi Kalpana K. Vakati, Jeffrey S. McNeil
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Publication number: 20240395338Abstract: Processing logic in a memory device receives a calibration scan command associated with the memory device. In response to the calibration scan command, execution of a set of read operations at a plurality of read voltage levels on the memory device is caused. In response to the calibration scan command, a set of bit counts is identified, where each bit count of the set of bit counts corresponds to a respective bin of a set of bins associated with the plurality of read voltage levels. Based on the bit count corresponding to each bin of the set of bins, a bin having a lowest bit count is identified.Type: ApplicationFiled: July 31, 2024Publication date: November 28, 2024Inventors: Eric N. Lee, Violante Moschiano, Jeffrey S. McNeil, James Fitzpatrick, Sivagnanam Parthasarathy, Kishore Kumar Muchherla, Patrick R. Khayat
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Patent number: 12147052Abstract: A head-mounted device includes a device housing, a support structure that is connected to the device housing to support the device housing with respect to a user, a display device that is connected to the device housing to display content, an optical system that is associated with the display device, and sensors that generate sensor output signals. The head-mounted device also includes a tension controller that determines a tensioning command based on the sensor output signals, and a tension adjuster that applies tension to the user according to the tensioning command in order to restrain motion of the device housing with respect to the user.Type: GrantFiled: October 17, 2023Date of Patent: November 19, 2024Assignee: APPLE INC.Inventors: Grant H. Mulliken, David A. Kalinowski, Brandon R. Neale, David A. Schmuck, Eric N. Vergo, Jae Hwang Lee
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Publication number: 20240379178Abstract: Control logic in a memory device identifies a set of memory cells in a block of a memory array, wherein the set of memory cells comprises two or more memory cells programmed during a program phase of a program operation and associated with a selected wordline of the memory array. The control logic further causes a program verify voltage to be applied to the selected wordline during a program verify phase of the program operation and performs concurrent sensing operations on the set of memory cells to determine whether each memory cell in the set of memory cells was programmed to at least the program verify voltage during the program phase of the program operation.Type: ApplicationFiled: July 22, 2024Publication date: November 14, 2024Inventors: Eric N. Lee, Tomoko Ogura Iwasaki
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Patent number: 12142343Abstract: Memory devices might include an array of memory cells, a plurality of access lines, and control logic. The array of memory cells includes a plurality of strings of series-connected memory cells. Each access line of the plurality of access lines is connected to a control gate of a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells. The control logic is configured to: open the array of memory cells for multiple read operations; read first page data from respective memory cells coupled to a selected access line of the plurality of access lines; read second page data from the respective memory cells coupled to the selected access line; and close the array of memory cells subsequent to reading the first page data and the second page data.Type: GrantFiled: August 11, 2023Date of Patent: November 12, 2024Assignee: Micron Technology, Inc.Inventors: Eric N. Lee, Kishore Kumar Muchherla, Jeffrey S. McNeil, Jung-Sheng Hoei
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Publication number: 20240361929Abstract: A second read command to read second data from an array of memory cells is detected. An initial voltage to be applied to at least one wordline coupled to at least a subset of the array of memory cells is caused prior to releasing a first data associated with a first read command stored in a page buffer. The initial voltage to increase to a target value is caused. The page buffer to sense the second data from a bitline coupled to a page of the subset of the array of memory cells is caused. The sensed second data out of the bitline into the page buffer is read responsive to determining that the first data has been released from the page buffer.Type: ApplicationFiled: July 10, 2024Publication date: October 31, 2024Inventors: Sundararajan Sankaranarayanan, Eric N. Lee
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Patent number: 12131060Abstract: Exemplary methods, apparatuses, and systems include a quick charge loss (QCL) mitigation manager for controlling writing data bits to a memory device. The QCL mitigation manager receives a first set of data bits for programming to memory. The QCL mitigation manager writes a first subset of data bits of the first set of data bits to a first memory block of the memory during a first pass of programming. The QCL mitigation manager writes a second subset of data bits of the first set of data bits to the first memory block during a second pass of programming in response to determining that the threshold delay is satisfied.Type: GrantFiled: July 25, 2022Date of Patent: October 29, 2024Assignee: MICRON TECHNOLOGY, INC.Inventors: Kishore Kumar Muchherla, Dung V. Nguyen, Dave Scott Ebsen, Tomoharu Tanaka, James Fitzpatrick, Huai-Yuan Tseng, Akira Goda, Eric N. Lee
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Patent number: 12111781Abstract: A memory device includes a memory array and processing logic, operatively coupled with the memory array, to perform operations including causing a data burst to be initiated by toggling a logical level of a control pin from a first level corresponding to a data burst inactive mode to a second level corresponding to a data burst active mode, wherein the data burst corresponds to a data transfer across an interface bus, causing the data burst to be suspended by toggling the logical level of the control pin from the second level to a third level corresponding to a data burst suspend mode, and causing the data burst to be resumed by toggling the logical level of the control pin from the third level to the second level.Type: GrantFiled: March 9, 2023Date of Patent: October 8, 2024Assignee: Micron Technology, Inc.Inventors: Eric N. Lee, Leonid Minz, Yoav Weinberg, Ali Feiz Zarrin Ghalam, Luigi Pilolli
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Patent number: 12105967Abstract: A system can include a processing device operatively coupled with the one or more memory devices, to perform operations that include writing data to the one or more memory devices and performing one or more scan operations on a management unit containing the data to determine a current value of a chosen data state metric. Each scan operation can be performed using a corresponding predetermined read-time parameter value. The operations can include determining whether the current value of the chosen data state metric satisfies a criterion, and can also include, responsive to determining that the current value of the chosen data state metric satisfies the criterion, selecting a remedial operation by determining whether redundancy metadata is included in a fault tolerant data stripe on the one or more memory devices. The operations can also include performing the remedial operation with respect to the management unit.Type: GrantFiled: August 24, 2022Date of Patent: October 1, 2024Assignee: Micron Technology, Inc.Inventors: Kishore Kumar Muchherla, Robert Loren O. Ursua, Sead Zildzic, Eric N. Lee, Jonathan S. Parry, Lakshmi Kalpana K. Vakati, Jeffrey S. McNeil
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Publication number: 20240312537Abstract: A request to execute a programming operation to program multiple sub-blocks including a first sub-block and a second sub-block of a memory device is identified. A first drive operation is executed to load first data into a first select gate drain (SGD) associated with the first sub-block. One or more program bias disturb mitigation operations are executed in association with a second drive operation to load second data into a second SGD associated with the second sub-block.Type: ApplicationFiled: March 14, 2024Publication date: September 19, 2024Inventors: Eric N. Lee, Tomoko Ogura Iwasaki, Alessio Urbani, Justin Bates
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Publication number: 20240312933Abstract: An apparatus is provided, comprising a substrate with a frontside and a backside opposite the frontside; control circuitry disposed over the frontside of the substrate; a memory array disposed over and electrically coupled to the control circuitry; a through-silicon via (TSV) disposed under the memory array, the TSV extending through the substrate from the control circuitry to the backside of the substrate; and a bond pad disposed on the backside of the substrate and electrically coupled to the control circuitry via the TSV.Type: ApplicationFiled: March 15, 2024Publication date: September 19, 2024Inventors: Eric N. Lee, Akira Goda
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Publication number: 20240312525Abstract: A request to execute a programming operation to program multiple sub-blocks including a first sub-block and a second sub-block of a memory device is identified. A first drive operation is executed to load first data into a first select gate drain (SGD) associated with the first sub-block. Following completion of the first drive operation, a second drive operation is executed to load second data into a second SGD associated with the second sub-block. Following completion of the second drive operation, a third drive operation is executed to re-load the first data into the first SGD.Type: ApplicationFiled: March 14, 2024Publication date: September 19, 2024Inventors: Eric N. Lee, Tomoko Ogura Iwasaki, Alessio Urbani, Justin Bates
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Publication number: 20240311307Abstract: A memory device includes a first memory array, a second memory array, and a page cache circuit coupled to the first memory array and the second memory array. The page cache circuit includes at least one set of concurrent resources and at least one shared resource, wherein the at least one set of concurrent resources are asynchronously and concurrently accessible by the first memory array and the second memory array, and wherein the at least one shared resource is accessible in a time-multiplexed fashion by the first memory array and the second memory array.Type: ApplicationFiled: May 22, 2024Publication date: September 19, 2024Inventors: Sundararajan Sankaranarayanan, Eric N. Lee
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Patent number: 12073895Abstract: Control logic in a memory device identifies a set of memory cells in a block of a memory array, wherein the set of memory cells comprises two or more memory cells programmed during a program phase of a program operation and associated with a selected wordline of the memory array. The control logic further causes a program verify voltage to be applied to the selected wordline during a program verify phase of the program operation and performs concurrent sensing operations on the set of memory cells to determine whether each memory cell in the set of memory cells was programmed to at least the program verify voltage during the program phase of the program operation.Type: GrantFiled: February 28, 2022Date of Patent: August 27, 2024Assignee: Micron Technology, Inc.Inventors: Eric N. Lee, Tomoko Ogura Iwasaki
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Patent number: 12073891Abstract: Processing logic in a memory device receives a command to execute a set of read operations having read voltage levels corresponding to a programming distribution associated with the memory device. A set of memory bit counts is determined, where each memory bit count corresponds to a respective bin of a set of bins associated with the multiple read voltage levels of the set of read operations. A valley center bin having a minimum memory bit count of the set of memory bit counts is determined. The processing logic determines that the minimum memory bit count of the valley center bin satisfies a condition and an adjusted read voltage level associated with the valley center bin is identified in response to the condition being satisfied.Type: GrantFiled: February 28, 2022Date of Patent: August 27, 2024Assignee: Micron Technology, Inc.Inventors: Eric N. Lee, Violante Moschiano, Jeffrey S. McNeil, James Fitzpatrick, Sivagnanam Parthasarathy, Kishore Kumar Muchherla, Patrick R. Khayat
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Patent number: 12061806Abstract: A second read command to read second data from an array of memory cells is detected. An initial voltage to be applied to at least one wordline coupled to at least a subset of the array of memory cells is caused prior to releasing a first data associated with a first read command stored in a page buffer. The initial voltage to increase to a target value is caused. The page buffer to sense the second data from a bitline coupled to a page of the subset of the array of memory cells is caused. The sensed second data out of the bitline into the page buffer is read responsive to determining that the first data has been released from the page buffer.Type: GrantFiled: July 6, 2022Date of Patent: August 13, 2024Assignee: Micron Technology, Inc.Inventors: Sundararajan Sankaranarayanan, Eric N. Lee
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Publication number: 20240248646Abstract: A method performed by a processing device receives a plurality of write operation requests, where each of the write operation requests specifies a respective one of the memory units, identifies one or more operating characteristic values, where each operating characteristic value reflects one or more memory access operations performed on a memory device, and determines whether the operating characteristic values satisfy one or more threshold criteria. Responsive to determining that the operating characteristic values satisfy the one or more threshold criteria, the method performs a plurality of write operations, where each of the write operations writes data to the respective one of the memory units, and performs a multiple-read scan operation subsequent to the plurality of write operations, where the multiple-read scan operation reads data from each of the memory units.Type: ApplicationFiled: April 1, 2024Publication date: July 25, 2024Inventors: Kishore Kumar Muchherla, Eric N. Lee, Jeffrey S. McNeil, Jonathan S. Parry, Lakshmi Kalpana Vakati
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Publication number: 20240231617Abstract: A memory device includes an array of memory cells and a controller configured to access the array of memory cells. The controller is further configured to program a first number of bits to a first memory cell of the array of memory cells and program a second number of bits to a second memory cell of the array of memory cells. The controller is further configured to following a period after programming the second number of bits to the second memory cell, merge at least a subset of the first number of bits stored in the first memory cell to the second number of bits stored in the second memory cell without erasing the second memory cell such that the second number of bits plus at least the subset of the first number of bits are stored in the second memory cell.Type: ApplicationFiled: March 21, 2024Publication date: July 11, 2024Applicant: MICRON TECHNOLOGY, INC.Inventors: Tomoharu Tanaka, Huai-Yuan Tseng, Dung V. Nguyen, Kishore Kumar Muchherla, Eric N. Lee, Akira Goda, James Fitzpatrick, Dave Ebsen
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Publication number: 20240231675Abstract: A memory system includes a ready busy pin coupled with a plurality of dice and a processing device coupled with the ready busy pin. The processing device is to perform controller operations including waiting to perform any status checks until after assertion of a pulse on a status indicator signal received from the ready busy pin; detecting the pulse being asserted is an extended pulse comprising at least a partial overlap of a first pulse asserted by a first die and a second pulse asserted by a second die of the plurality of dice; initiating a polling delay period in response to detecting assertion of the extended pulse, wherein the polling delay period is greater than a pulse width of the first pulse; and initiating a first status check of dice operations being performed by the plurality of dice in response to detecting expiration of the polling delay period.Type: ApplicationFiled: March 20, 2024Publication date: July 11, 2024Inventors: Eric N. Lee, Dheeraj Srinivasan
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Patent number: 12019550Abstract: A memory device includes a first memory array, a second memory array, and a page cache circuit coupled to the first memory array and the second memory array. The page cache circuit includes at least one set of concurrent resources and at least one shared resource, wherein the at least one set of concurrent resources are asynchronously and concurrently accessible by the first memory array and the second memory array, and wherein the at least one shared resource is accessible in a time-multiplexed fashion by the first memory array and the second memory array.Type: GrantFiled: December 10, 2021Date of Patent: June 25, 2024Assignee: Micron Technology, Inc.Inventors: Sundararajan Sankaranarayanan, Eric N. Lee