Patents by Inventor Eric Nequist
Eric Nequist has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11157670Abstract: An integrated circuit and a method for designing an IC where the smallest repeatable block is selected, designed and tested to span across multiple die levels. The block is configured to be timing closed at the block level thereby reducing the overall complexity of the design and avoiding the limiting effects of the constrained EDA tools. The block may subsequently be repeated on multiple die to be stacked in an IC.Type: GrantFiled: May 22, 2020Date of Patent: October 26, 2021Assignee: Xcelsis CorporationInventors: Javier A Delacruz, Eric Nequist, Jung Ko, Kenneth Duong
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Publication number: 20200356714Abstract: An integrated circuit and a method for designing an IC where the smallest repeatable block is selected, designed and tested to span across multiple die levels. The block is configured to be timing closed at the block level thereby reducing the overall complexity of the design and avoiding the limiting effects of the constrained EDA tools. The block may subsequently be repeated on multiple die to be stacked in an IC.Type: ApplicationFiled: May 22, 2020Publication date: November 12, 2020Applicant: Xcelsis CorporationInventors: Javier A. DELACRUZ, Eric NEQUIST, Jung KO, Kenneth DUONG
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Patent number: 10664564Abstract: An integrated circuit and a method for designing an IC where the smallest repeatable block is selected, designed and tested to span across multiple die levels. The block is configured to be timing closed at the block level thereby reducing the overall complexity of the design and avoiding the limiting effects of the constrained EDA tools. The block may subsequently be repeated on multiple die to be stacked in an IC.Type: GrantFiled: June 22, 2018Date of Patent: May 26, 2020Assignee: Xcelsis CorporationInventors: Javier A Delacruz, Eric Nequist, Jung Ko, Kenneth Duong
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Publication number: 20190392104Abstract: An integrated circuit and a method for designing an IC where the smallest repeatable block is selected, designed and tested to span across multiple die levels. The block is configured to be timing closed at the block level thereby reducing the overall complexity of the design and avoiding the limiting effects of the constrained EDA tools. The block may subsequently be repeated on multiple die to be stacked in an IC.Type: ApplicationFiled: June 22, 2018Publication date: December 26, 2019Applicant: Xcelsis CorporationInventors: Javier A DELACRUZ, Eric NEQUIST, Jung KO, Kenneth DUONG
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Patent number: 8635574Abstract: An improved method and system for performing extraction on an integrated circuit design is disclosed. Extraction may be performed at granularities much smaller than the entire IC design, in which a halo is used to identify a geometric volume surrounding an object of interest to identify neighboring objects and generate an electrical model. The extraction approach can be taken for Islands, Nets, as well as other granularities within the design. Re-extraction of a design can occur at granularities smaller than a net. Some approaches utilize Island-stitching to replace an island within a net. An approach is also described for improving cross-references for cross-coupled objects.Type: GrantFiled: January 7, 2011Date of Patent: January 21, 2014Assignee: Cadence Design Systems, Inc.Inventors: Eric Nequist, Richard Brashears, Matthew A. Liberty, Michael C. McSherry
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Patent number: 8631363Abstract: A method and mechanism is disclosed for identifying and tracking nets in an electrical design. A hierarchical design does not have to be flattened to perform the operation of identifying and tracking nets. To identify sets of connected shapes, instead of having to unfold the entire design hierarchy, only the specific instances of shapes falling within the geometric bounds of shapes identified as being part of a net needs to be unfolded to perform the search. When composing the list of nets for a hierarchical design, the unfolded shapes at other hierarchical levels of the design can be derived based upon virtual terminal structures that implicitly references nets and objects at other levels.Type: GrantFiled: November 21, 2011Date of Patent: January 14, 2014Assignee: Cadence Design Systems, Inc.Inventor: Eric Nequist
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Method and system for implementing efficient locking to facilitate parallel processing of IC designs
Patent number: 8438512Abstract: Disclosed is an improved method and system for implementing parallelism for execution of electronic design automation (EDA) tools, such as layout processing tools. Examples of EDA layout processing tools are placement and routing tools. Efficient locking mechanism are described for facilitating parallel processing and to minimize blocking.Type: GrantFiled: August 30, 2011Date of Patent: May 7, 2013Assignee: Cadence Design Systems, Inc.Inventors: David Cross, Eric Nequist -
Patent number: 8392864Abstract: Disclosed is a method, system, and computer program product for implementing model-based floorplanning, layout, placement, and routing. Models are used to guide the placement and routing of polygons on the IC layout based upon predictions of manufacturing variations.Type: GrantFiled: December 27, 2010Date of Patent: March 5, 2013Assignee: Cadence Design Systems, Inc.Inventors: David White, Eric Nequist
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Patent number: 8386975Abstract: An improved method, system, user interface, and computer program product is described for using a memory and learning component to improve capacitance and resistance estimates based on the types of layouts and devices being evaluated. According to some approaches, a learning component is implemented that uses recommended test sets from the evaluation component to automatically test the extraction estimates against the field solver. Variability models from manufacturing or electrical analysis may also be used to select a series of objects (unique conductor geometries) that make up a conduction path or net or specific conductor geometries for evaluation and additional learning improvement.Type: GrantFiled: December 26, 2008Date of Patent: February 26, 2013Assignee: Cadence Design Systems, Inc.Inventors: David White, Matthew Liberty, Eric Nequist, Michael McSherry
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Patent number: 8375342Abstract: An improved method and system for performing extraction on an integrated circuit design is disclosed. Extraction may be performed at granularities much smaller than the entire IC design, in which a halo is used to identify a geometric volume surrounding an object of interest to identify neighboring objects and generate an electrical model. The extraction approach can be taken for Islands, Nets, as well as other granularities within the design. Re-extraction of a design can occur at granularities smaller than a net. Some approaches utilize Island-stitching to replace an island within a net. An approach is also described for improving cross-references for cross-coupled objects.Type: GrantFiled: January 7, 2011Date of Patent: February 12, 2013Assignee: Cadence Design Systems, Inc.Inventors: Eric Nequist, Richard Brashears, Matthew A. Liberty, Michael C. McSherry
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Patent number: 8316331Abstract: An improved method and system for stitching one or more islands of an integrated circuit design is disclosed. Multiple connected island objects in the IC design are first identified. At least one of the multiple identified connected island objects is then modified to form a modified island object. The modified island object may then be stitched into the multiple identified connected island objects. In some embodiments, stitching a modified island object may be implemented by tracking the endpoint(s), port(s), or node(s) of the connected island object being modified and stitched.Type: GrantFiled: January 7, 2011Date of Patent: November 20, 2012Assignee: Cadence Design Systems, Inc.Inventors: Eric Nequist, Richard Brashears, Matthew A. Liberty, Michael C. McSherry
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Publication number: 20120131524Abstract: A method and mechanism is disclosed for identifying and tracking nets in an electrical design. A hierarchical design does not have to be flattened to perform the operation of identifying and tracking nets. To identify sets of connected shapes, instead of having to unfold the entire design hierarchy, only the specific instances of shapes falling within the geometric bounds of shapes identified as being part of a net needs to be unfolded to perform the search. When composing the list of nets for a hierarchical design, the unfolded shapes at other hierarchical levels of the design can be derived based upon virtual terminal structures that implicitly references nets and objects at other levels.Type: ApplicationFiled: November 21, 2011Publication date: May 24, 2012Applicant: CADENCE DESIGN SYSTEMS, INC.Inventor: Eric Nequist
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Patent number: 8136060Abstract: A method and mechanism is disclosed for identifying and tracking nets in an electrical design. A hierarchical design does not have to be flattened to perform the operation of identifying and tracking nets. To identify sets of connected shapes, instead of having to unfold the entire design hierarchy, only the specific instances of shapes falling within the geometric bounds of shapes identified as being part of a net needs to be unfolded to perform the search. When composing the list of nets for a hierarchical design, the unfolded shapes at other hierarchical levels of the design can be derived based upon virtual terminal structures that implicitly references nets and objects at other levels.Type: GrantFiled: December 29, 2009Date of Patent: March 13, 2012Assignee: Cadence Design Systems, Inc.Inventor: Eric Nequist
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METHOD AND SYSTEM FOR IMPLEMENTING EFFICIENT LOCKING TO FACILITATE PARALLEL PROCESSING OF IC DESIGNS
Publication number: 20110314432Abstract: Disclosed is an improved method and system for implementing parallelism for execution of electronic design automation (EDA) tools, such as layout processing tools. Examples of EDA layout processing tools are placement and routing tools. Efficient locking mechanism are described for facilitating parallel processing and to minimize blocking.Type: ApplicationFiled: August 30, 2011Publication date: December 22, 2011Applicant: CADENCE DESIGN SYSTEMS, INC.Inventors: David Cross, Eric Nequist -
Patent number: 8069426Abstract: A method and mechanism is disclosed for identifying and tracking nets in an electrical design. A hierarchical design does not have to be flattened to perform the operation of identifying and tracking nets. To identify sets of connected shapes, instead of having to unfold the entire design hierarchy, only the specific instances of shapes falling within the geometric bounds of shapes identified as being part of a net needs to be unfolded to perform the search. When composing the list of nets for a hierarchical design, the unfolded shapes at other hierarchical levels of the design can be derived based upon virtual terminal structures that implicitly references nets and objects at other levels.Type: GrantFiled: September 30, 2008Date of Patent: November 29, 2011Assignee: Cadence Design Systems, Inc.Inventor: Eric Nequist
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Method and system for implementing efficient locking to facilitate parallel processing of IC designs
Patent number: 8010917Abstract: Disclosed is an improved method and system for implementing parallelism for execution of electronic design automation (EDA) tools, such as layout processing tools. Examples of EDA layout processing tools are placement and routing tools. Efficient locking mechanism are described for facilitating parallel processing and to minimize blocking.Type: GrantFiled: December 26, 2007Date of Patent: August 30, 2011Assignee: Cadence Design Systems, Inc.Inventors: David Cross, Eric Nequist -
Patent number: 7971173Abstract: Disclosed is an improved method, system, and article of manufacture for implementing routing for an electrical circuit and chip design. A routing architecture can be represented as a spectrum of different granular routing levels. Instead of routing based upon area, routing can be performed for specific routes or portions of routes. Different types of representation or levels of abstraction for the routing can be used for the same net or route. Partial topological reconfiguration, refinement, or rip-up can be performed for a portion of the integrated circuit design, where the portion is smaller than an entire route or net. Non-uniform levels of routing activities or resources may be applied to route the design. Prioritization may be used to route certain portions of the design with greater levels of detail, abstraction, or resources than other portions of the design.Type: GrantFiled: April 27, 2007Date of Patent: June 28, 2011Assignee: Cadence Design Systems, Inc.Inventors: Richard Brashears, Eric Nequist
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Publication number: 20110093826Abstract: Disclosed is a method, system, and computer program product for implementing model-based floorplanning, layout, placement, and routing. Models are used to guide the placement and routing of polygons on the IC layout based upon predictions of manufacturing variations.Type: ApplicationFiled: December 27, 2010Publication date: April 21, 2011Applicant: CADENCE DESIGN SYSTEMS, INC.Inventors: David WHITE, Eric NEQUIST
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Patent number: 7904862Abstract: A method and mechanism is disclosed for identifying spacing and clearance based rule violations in an IC design. Shadows are employed to identify spacing and clearance based rule violations. The shadow approach of is particularly useful to identify width-dependent spacing and clearance violations, while avoiding false positives that exist with alternate approaches. The embodiments can be used with any type, configuration, or shape of layout objects.Type: GrantFiled: December 26, 2007Date of Patent: March 8, 2011Assignee: Cadence Design Systems, Inc.Inventor: Eric Nequist
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Patent number: 7870517Abstract: An improved method and system for performing extraction on an integrated circuit design is disclosed. Extraction can be performed at granularities much smaller than the entire IC design, in which a halo is used to identify a geometric volume surrounding an object of interest to identify neighboring objects and generate an electrical model. The extraction approach can be taken for Islands, Nets, as well as other granularities within the design. Re-extraction of a design can occur at granularities smaller than a net. Some approaches utilize Island-stitching to replace an island within a net. An approach is also described for improving cross-references for cross-coupled objects.Type: GrantFiled: April 27, 2007Date of Patent: January 11, 2011Assignee: Cadence Design Systems, Inc.Inventors: Eric Nequist, Richard Brashears, Matthew A. Liberty, Michael C. McSherry