Patents by Inventor Eric Nestler

Eric Nestler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9698759
    Abstract: An approach to time domain filtering uses a passive charge sharing approach to implement an infinite impulse response filter. Delayed samples of an input signal are stored as charges on capacitors of a first array of capacitors, and delayed samples of the output signal are stored as charges on capacitors of a second array of capacitors. Outputs are determined by passively coupling capacitors of the first and second arrays to one another, and determining the output according to a total charge on the coupled capacitors. In some examples, a gain is applied to the total charge prior to storing the output on the second array of capacitors. In some examples, a charge scaling circuit is applied to the charges stored on the arrays prior to coupling capacitors to form the output.
    Type: Grant
    Filed: May 5, 2014
    Date of Patent: July 4, 2017
    Assignee: ANALOG DEVICES, INC.
    Inventors: Eric Nestler, Jeffrey Venuti, Vladimir Zlatkovic, Kartik Nanda
  • Patent number: 9479866
    Abstract: Microphone stages in a microphone array may be coupled together in a daisy chain. Each stage may include a microphone, an analog to digital converter, a decimation unit, a receiver, an adder, and a transmitter. The converter may convert analog audio microphone signals into digital codes that may be decimated. The adder may add decimated digital codes in each stage to a cumulative sum of decimated digital codes from prior stages. This new sum may be transmitted to the next microphone stage, where the adder may add the decimated digital codes from that stage to the cumulative sum. A serial interface may be used to connect the transmitters and receivers of each of the stages. The serial interface may be used to transmit the cumulative sum of decimated digital codes between the stages. The serial interface may also be used to transmit configuration data between the stages.
    Type: Grant
    Filed: March 23, 2012
    Date of Patent: October 25, 2016
    Assignee: Analog Devices, Inc.
    Inventors: Robert Adams, David Hossack, Benjamin Vigoda, Eric Nestler, Mira Wilczek
  • Patent number: 9312831
    Abstract: In one aspect, reduced power consumption and/or circuit area of a discrete time analog signal processing module is achieved in an approach that makes use of entirely, or largely, passive charge sharing circuitry, which may include configurable (e.g., after fabrication, at runtime) multiplicative scaling stages that do not require active devices in the signal path. In some examples, multiplicative coefficients are represented digitally, and are transformed to configure the reconfigurable circuitry to achieve a linear relationship between a desired coefficient and a degree of charge transfer. In some examples, multiple successive charge sharing phases are used to achieve a desired multiplicative effect that provides a large dynamic range of coefficients without requiring a commensurate range of sizes of capacitive elements. The scaling circuits can be combined to form configurable time domain or frequency domain filters.
    Type: Grant
    Filed: October 1, 2013
    Date of Patent: April 12, 2016
    Assignee: ANALOG DEVICES, INC.
    Inventors: Eric Nestler, Vladimir Zlatkovic, Jeffrey Venuti
  • Publication number: 20150381146
    Abstract: An approach to time domain filtering uses a passive charge sharing approach to implement an infinite impulse response filter. Delayed samples of an input signal are stored as charges on capacitors of a first array of capacitors, and delayed samples of the output signal are stored as charges on capacitors of a second array of capacitors. Outputs are determined by passively coupling capacitors of the first and second arrays to one another, and determining the output according to a total charge on the coupled capacitors. In some examples, a gain is applied to the total charge prior to storing the output on the second array of capacitors. In some examples, a charge scaling circuit is applied to the charges stored on the arrays prior to coupling capacitors to form the output.
    Type: Application
    Filed: May 5, 2014
    Publication date: December 31, 2015
    Applicant: Analog Devices, Inc.
    Inventors: Eric Nestler, Jeffrey Venuti, Vladimir Zlatkovic, Kartik Nanda
  • Patent number: 9218318
    Abstract: Some general aspects of the invention relate to a circuit and to a method for analog computation, for example, using switched capacitor integrated circuits. In some examples, a circuit includes a first group of capacitors and a second group of capacitors that may store charges during circuit operation. The first and/or the second group of capacitors may include multiple disjoint subsets of capacitors. An input circuit is provided for receiving a set of input signals and for inducing a charge on each of some or all capacitors in the first group of capacitors according to a corresponding input signal. Switches, for example, transistors controlled by a sequence of clock signals, are used to couple different sets of capacitors. Different configurations of the switches are used to form different sets of the capacitors among which charge can redistribute.
    Type: Grant
    Filed: May 29, 2012
    Date of Patent: December 22, 2015
    Assignee: Analog Devices, Inc.
    Inventors: Eric Nestler, Vladimir Zlatkovic
  • Patent number: 9160308
    Abstract: A signal processing device has a first discrete time analog signal processing section, which has an input, an output, a plurality of charge storage elements, and plurality of switch elements coupling the charge storage elements. The device has a controller coupled to the first signal processing section configured to couple different subsets of the charge elements of the first signal processing section in successive operating phases to apply a signal processing function to an analog signal presented at the input of the first signal processing section and provide a result of the applying of the signal processing function as an analog signal to the output of first signal processing section. The signal processing function of the first signal processing section comprises a combination of a filtering function operating at a first sampling rate and one or more modulation functions operating at corresponding modulation rates lower than the first sampling rate.
    Type: Grant
    Filed: December 6, 2013
    Date of Patent: October 13, 2015
    Assignee: Analog Devices, Inc.
    Inventor: Eric Nestler
  • Publication number: 20150162894
    Abstract: A signal processing device has a first discrete time analog signal processing section, which has an input, an output, a plurality of charge storage elements, and plurality of switch elements coupling the charge storage elements. The device has a controller coupled to the first signal processing section configured to couple different subsets of the charge elements of the first signal processing section in successive operating phases to apply a signal processing function to an analog signal presented at the input of the first signal processing section and provide a result of the applying of the signal processing function as an analog signal to the output of first signal processing section. The signal processing function of the first signal processing section comprises a combination of a filtering function operating at a first sampling rate and one or more modulation functions operating at corresponding modulation rates lower than the first sampling rate.
    Type: Application
    Filed: December 6, 2013
    Publication date: June 11, 2015
    Applicant: Analog Devices, Inc.
    Inventor: Eric Nestler
  • Patent number: 9036420
    Abstract: A storage device includes a storage array having a group of storage elements. Each storage element can written to a discrete set of physical states. A read circuit selects one or more storage elements and generates, for each selected storage element, an analog signal representative of the physical state of the selected storage element. A signal processing circuit processes the analog signal to generate a plurality of outputs, with each output representing a degree of an association of the selected storage element with a different subset of one or more of the discrete set of physical states.
    Type: Grant
    Filed: May 15, 2012
    Date of Patent: May 19, 2015
    Assignee: ANALOG DEVICES, INC.
    Inventors: Benjamin Vigoda, Jeffrey Bernstein, Jeffrey Venuti, Alexander Alexeyev, Eric Nestler, David Reynolds, William Bradley, Vladimir Zlatkovic
  • Publication number: 20140233773
    Abstract: In one aspect, reduced power consumption and/or circuit area of a discrete time analog signal processing module is achieved in an approach that makes use of entirely, or largely, passive charge sharing circuitry, which may include configurable (e.g., after fabrication, at runtime) multiplicative scaling stages that do not require active devices in the signal path. In some examples, multiplicative coefficients are represented digitally, and are transformed to configure the reconfigurable circuitry to achieve a linear relationship between a desired coefficient and a degree of charge transfer. In some examples, multiple successive charge sharing phases are used to achieve a desired multiplicative effect that provides a large dynamic range of coefficients without requiring a commensurate range of sizes of capacitive elements. The scaling circuits can be combined to form configurable time domain or frequency domain filters.
    Type: Application
    Filed: October 1, 2013
    Publication date: August 21, 2014
    Applicant: Analog Devices, Inc.
    Inventors: Eric Nestler, Vladimir Zlatkovic, Jeffrey Venuti
  • Patent number: 8736361
    Abstract: A filter provides high-pass coupling between circuits. The filter includes charge storage elements and switch elements coupling the charge storage elements. A controller is coupled to the switch elements for sequencing configurations of the switch elements in phases for each of a succession of sample periods to perform a time sampled continuous value signal processing of the input signal to form the processed signal. The sequenced configurations include a configuration in which a charge representing a value of the input signal is stored on a multiple of the charge storage elements, a configuration in which charge storage elements are coupled with the switch elements, and a set of one or more configurations that implement a scaling of a charge on one of the charge storage elements to be on one or more of the charge storage elements.
    Type: Grant
    Filed: December 4, 2012
    Date of Patent: May 27, 2014
    Assignee: Analog Devices, Inc.
    Inventors: Eric Nestler, Gustavo Castro
  • Patent number: 8717094
    Abstract: An approach to time domain filtering uses a passive charge sharing approach to implement an infinite impulse response filter. Delayed samples of an input signal are stored as charges on capacitors of a first array of capacitors, and delayed samples of the output signal are stored as charges on capacitors of a second array of capacitors. Outputs are determined by passively coupling capacitors of the first and second arrays to one another, and determining the output according to a total charge on the coupled capacitors. In some examples, a gain is applied to the total charge prior to storing the output on the second array of capacitors. In some examples, a charge scaling circuit is applied to the charges stored on the arrays prior to coupling capacitors to form the output.
    Type: Grant
    Filed: June 6, 2012
    Date of Patent: May 6, 2014
    Assignee: Analog Devices, Inc.
    Inventors: Eric Nestler, Jeffrey Venuti, Vladimir Zlatkovic, Kartik Nanda
  • Patent number: 8547272
    Abstract: In one aspect, reduced power consumption and/or circuit area of a discrete time analog signal processing module is achieved in an approach that makes use of entirely, or largely, passive charge sharing circuitry, which may include configurable (e.g., after fabrication, at runtime) multiplicative scaling stages that do not require active devices in the signal path. In some examples, multiplicative coefficients are represented digitally, and are transformed to configure the reconfigurable circuitry to achieve a linear relationship between a desired coefficient and a degree of charge transfer. In some examples, multiple successive charge sharing phases are used to achieve a desired multiplicative effect that provides a large dynamic range of coefficients without requiring a commensurate range of sizes of capacitive elements. The scaling circuits can be combined to form configurable time domain or frequency domain filters.
    Type: Grant
    Filed: August 18, 2011
    Date of Patent: October 1, 2013
    Assignee: Analog Devices, Inc.
    Inventors: Eric Nestler, Vladimir Zlatkovic, Jeffrey Venuti
  • Publication number: 20130207827
    Abstract: In one aspect, reduced power consumption and/or circuit area of a discrete time analog signal processing module is achieved in an approach that makes use of entirely, or largely, passive charge sharing circuitry, which may include configurable (e.g., after fabrication, at runtime) multiplicative scaling stages that do not require active devices in the signal path. In some examples, multiplicative coefficients are represented digitally, and are transformed to configure the reconfigurable circuitry to achieve a linear relationship between a desired coefficient and a degree of charge transfer. In some examples, multiple successive charge sharing phases are used to achieve a desired multiplicative effect that provides a large dynamic range of coefficients without requiring a commensurate range of sizes of capacitive elements. The scaling circuits can be combined to form configurable time domain or frequency domain filters.
    Type: Application
    Filed: August 18, 2011
    Publication date: August 15, 2013
    Applicant: Analog Devices, Inc.
    Inventors: Eric Nestler, Vladimir Zlatkovic, Jeffrey Venuti
  • Patent number: 8456463
    Abstract: A low voltage driver for a higher voltage LCD includes a plurality of LCD drive bias voltage input-terminals; an LCD drive voltage output terminal; an input transistor switching circuit having at least one switch for each LCD drive bias voltage for selecting one of the bias voltages; an output transistor switching circuit, responsive to the input transistor switching circuit, for applying the selected one of the bias voltages to the LCD drive voltage output terminal, the transistors of the switching circuits having a predetermined breakdown voltage; a level shifter for providing switching voltages counterpart to the plurality of bias voltages; a logic circuit for enabling the first transistor switching circuit to select a one of the bias voltages and applying a set of counterpart switching voltages to the input and output transistor switching circuits for connecting the selected one of the bias voltages to the output terminal and applying a set of switching voltages to the input and output switching circuits
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: June 4, 2013
    Assignee: Analog Devices, Inc.
    Inventors: Abhishek Bandyopadhyay, Eric Nestler, Michael A. Ashburn, Jr.
  • Publication number: 20130120058
    Abstract: A filter provides high-pass coupling between circuits. The filter includes charge storage elements and switch elements coupling the charge storage elements. A controller is coupled to the switch elements for sequencing configurations of the switch elements in phases for each of a succession of sample periods to perform a time sampled continuous value signal processing of the input signal to form the processed signal. The sequenced configurations include a configuration in which a charge representing a value of the input signal is stored on a multiple of the charge storage elements, a configuration in which charge storage elements are coupled with the switch elements, and a set of one or more configurations that implement a scaling of a charge on one of the charge storage elements to be on one or more of the charge storage elements.
    Type: Application
    Filed: December 4, 2012
    Publication date: May 16, 2013
    Inventors: Eric Nestler, Gustavo Castro
  • Publication number: 20130121504
    Abstract: Microphone stages in a microphone array may be coupled together in a daisy chain. Each stage may include a microphone, an analog to digital converter, a decimation unit, a receiver, an adder, and a transmitter. The converter may convert analog audio microphone signals into digital codes that may be decimated. The adder may add decimated digital codes in each stage to a cumulative sum of decimated digital codes from prior stages. This new sum may be transmitted to the next microphone stage, where the adder may add the decimated digital codes from that stage to the cumulative sum. A serial interface may be used to connect the transmitters and receivers of each of the stages. The serial interface may be used to transmit the cumulative sum of decimated digital codes between the stages. The serial interface may also be used to transmit configuration data between the stages.
    Type: Application
    Filed: March 23, 2012
    Publication date: May 16, 2013
    Applicant: ANALOG DEVICES, INC.
    Inventors: Robert ADAMS, David HOSSACK, Benjamin VIGODA, Eric NESTLER, Mira WILCZEK
  • Publication number: 20130094298
    Abstract: A storage device includes a storage array having a group of storage elements. Each storage element can written to a discrete set of physical states. A read circuit selects one or more storage elements and generates, for each selected storage element, an analog signal representative of the physical state of the selected storage element. A signal processing circuit processes the analog signal to generate a plurality of outputs, with each output representing a degree of an association of the selected storage element with a different subset of one or more of the discrete set of physical states.
    Type: Application
    Filed: May 15, 2012
    Publication date: April 18, 2013
    Applicant: Analog Devices, Inc.
    Inventors: Benjamin Vigoda, Eric Nestler, Jeffrey Bernstein, David Reynolds, Alexander Alexeyev, Jeffrey Venuti, William Bradley, Vladimir Ziatkovic
  • Publication number: 20130080497
    Abstract: Some general aspects of the invention relate to a circuit and to a method for analog computation, for example, using switched capacitor integrated circuits. In some examples, a circuit includes a first group of capacitors and a second group of capacitors that may store charges during circuit operation. The first and/or the second group of capacitors may include multiple disjoint subsets of capacitors. An input circuit is provided for receiving a set of input signals and for inducing a charge on each of some or all capacitors in the first group of capacitors according to a corresponding input signal. Switches, for example, transistors controlled by a sequence of clock signals, are used to couple different sets of capacitors. Different configurations of the switches are used to form different sets of the capacitors among which charge can redistribute.
    Type: Application
    Filed: May 29, 2012
    Publication date: March 28, 2013
    Applicant: Analog Devices, Inc.
    Inventors: Eric Nestler, Vladimir Zlatkovic
  • Publication number: 20120306569
    Abstract: An approach to time domain filtering uses a passive charge sharing approach to implement an infinite impulse response filter. Delayed samples of an input signal are stored as charges on capacitors of a first array of capacitors, and delayed samples of the output signal are stored as charges on capacitors of a second array of capacitors. Outputs are determined by passively coupling capacitors of the first and second arrays to one another, and determining the output according to a total charge on the coupled capacitors. In some examples, a gain is applied to the total charge prior to storing the output on the second array of capacitors. In some examples, a charge scaling circuit is applied to the charges stored on the arrays prior to coupling capacitors to form the output.
    Type: Application
    Filed: June 6, 2012
    Publication date: December 6, 2012
    Applicant: Analog Devices, Inc.
    Inventors: Eric Nestler, Jeffrey Venuti, Vladimir Zlatkovic, Kartik Nanda
  • Patent number: 8188753
    Abstract: Some general aspects of the invention relate to a circuit and to a method for analog computation, for example, using switched capacitor integrated circuits. In some examples, a circuit includes a first group of capacitors and a second group of capacitors that may store charges during circuit operation. The first and/or the second group of capacitors may include multiple disjoint subsets of capacitors. An input circuit is provided for receiving a set of input signals and for inducing a charge on each of some or all capacitors in the first group of capacitors according to a corresponding input signal. Switches, for example, transistors controlled by a sequence of clock signals, are used to couple different sets of capacitors. Different configurations of the switches are used to form different sets of the capacitors among which charge can redistribute.
    Type: Grant
    Filed: August 21, 2009
    Date of Patent: May 29, 2012
    Assignee: Analog Devices, Inc.
    Inventors: Eric Nestler, Vladimir Zlatkovic